PIC32MX664F064LT-I/PT Microchip Technology Inc., PIC32MX664F064LT-I/PT Datasheet - Page 94

• Manufacturer Part Number: PIC32MX664F064LT-I/PT
• Description: 100 TQFP 12X12X1MM T/R, 100 PINS, 64KB FLASH, 32KB RAM, 80 MHZ, USB, ETHERNET, 4
• Manufacturer: Microchip Technology Inc.

Specifications of PIC32MX664F064LT-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: I2C/SPI/UART/USB
• Memory Type: Flash
• Number Of Bits: 32
• Package Type: 100-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 32K Bytes
• Speed: 80 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 4-28:
TABLE 4-29:
Legend:
Note
Legend:
Note
60C0
60D0
60C0
60D0 PORTD
60E0
60F0
60E0
60F0
1:
1:
PORTD
TRISD
ODCD
TRISD
ODCD
LATD
LATD
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
TRISD15
ODCD15
31/15
LAT15
RD15
31/15
—
—
—
—
—
—
—
—
—
—
—
—
TRISD14
ODCD14
LAT14
30/14
RD14
30/14
—
—
—
—
—
—
—
—
—
—
—
—
TRISD13
ODCD13
LAT13
29/13
RD13
29/13
—
—
—
—
—
—
—
—
—
—
—
—
TRISD12
ODCD12
28/12
LAT12
RD12
28/12
—
—
—
—
—
—
—
—
—
—
—
—
TRISD11
ODCD11
LATD11
TRISD11
ODCD11
LATD11
27/11
RD11
27/11
RD11
—
—
—
—
—
—
—
—
TRISD10
ODCD10
TRISD10
ODCD10
LATD10
LATD10
26/10
RD10
26/10
RD10
—
—
—
—
—
—
—
—
TRISD9
ODCD9
TRISD9
ODCD9
LATD9
LATD9
25/9
RD9
25/9
RD9
—
—
—
—
—
—
—
—
TRISD8
ODCD8
TRISD8
LATD8
ODCD8
LATD8
24/8
RD8
24/8
RD8
—
—
—
—
—
—
—
—
Bits
Bits
TRISD7
ODCD7
TRISD7
ODCD7
LATD7
LATD7
23/7
RD7
23/7
RD7
—
—
—
—
—
—
—
—
TRISD6
ODCD6
LATD6
TRISD6
ODCD6
LATD6
22/6
RD6
22/6
RD6
—
—
—
—
—
—
—
—
(1)
TRISD5
ODCD5
TRISD5
ODCD5
LATD5
LATD5
21/5
RD5
21/5
RD5
—
—
—
—
—
—
—
—
TRISD4
ODCD4
TRISD4
ODCD4
LATD4
LATD4
20/4
RD4
20/4
RD4
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
TRISD3
ODCD3
TRISD3
LATD3
ODCD3
LATD3
19/3
RD3
19/3
RD3
—
—
—
—
—
—
—
—
(1)
TRISD2
ODCD2
TRISD2
ODCD2
LATD2
LATD2
18/2
RD2
18/2
RD2
—
—
—
—
—
—
—
—
TRISD1
ODCD1
LATD1
TRISD1
ODCD1
LATD1
17/1
RD1
17/1
RD1
—
—
—
—
—
—
—
—
TRISD0
ODCD0
TRISD0
ODCD0
LATD0
LATD0
16/0
RD0
16/0
RD0
—
—
—
—
for more
for more
—
—
—
—
0000
FFFF
0000
xxxx
0000
xxxx
0000
0000
0000
0FFF
0000
xxxx
0000
xxxx
0000
0000