K4S643232H-TI70 Samsung Semiconductor, K4S643232H-TI70 Datasheet

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K4S643232H-TI70

Manufacturer Part Number
K4S643232H-TI70
Description
Manufacturer
Samsung Semiconductor
Datasheet

Specifications of K4S643232H-TI70

Lead Free Status / Rohs Status
Not Compliant
K4S643232H
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
* Samsung Electronics reserves the right to change products or specification without notice.
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
2M x 32 SDRAM
86 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.2
April 2006
- 1 -
Rev. 1.2 April 2006
SDRAM

Related parts for K4S643232H-TI70

K4S643232H-TI70 Summary of contents

Page 1

... K4S643232H SDRAM 86 TSOP-II with Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...

Page 2

... K4S643232H Revision History Revision Month Year 0.0 October 2003 0.1 November 2003 1.1 August 2004 1.2 April 2006 - Preliminary spec First release. - Final spec release. - Corrected typo. - Applied now format and corrected typo SDRAM History Rev. 1.2 April 2006 ...

Page 3

... RoHS compliant GENERAL DESCRIPTION The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications ...

Page 4

... K4S643232H Package Physical Dimension #86 #1 0.10 MAX 0.004 0. 0.024 #44 #43 22.62 MAX 0.891 22.22 ± 0.10 0.21 0.875 ± 0.004 0.008 +0.07 0.20 0.50 -0.03 +0.003 0.0197 0.0079 -0.001 86Pin TSOP Package Dimension - 4 - SDRAM 0~8°C 0.25 TYP 0.010 +0.075 0.125 -0 ...

Page 5

... K4S643232H FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE Data Input Register 512K x 32 512K x 32 512K x 32 512K x 32 Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS SDRAM LWCBR DQM Rev ...

Page 6

... K4S643232H PIN CONFIGURATION (Top view) V DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 N.C V DQM0 WE CAS RAS CS N.C BA0 BA1 A10/ DQM2 V N.C DQ16 V SSQ DQ17 DQ18 V DDQ DQ19 DQ20 V SSQ DQ21 DQ22 V DDQ DQ23 DQ15 DQ14 ...

Page 7

... K4S643232H PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable Address 0 10 BA0,1 Bank select address RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 3 Data input/output mask DQ ~ Data input/output Power supply/ground Data output power/ground ...

Page 8

... K4S643232H ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. ...

Page 9

... Refresh Current ICC5 Self Refresh Current ICC6 Notes : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232H-UC 5. K4S643232H- 70° IH(min) Test Condition Burst Length =1 tRC ≥ tRC(min), tCC ≥ tCC(min 0mA CKE ≤ VIL(max), tCC = 15ns CKE & ...

Page 10

... K4S643232H AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200Ω Output 50pF 870Ω (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...

Page 11

... K4S643232H AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS Latency=3 CLK cycle time CAS Latency=2 CAS Latency=3 CLK to valid output delay CAS Latency=2 Output data hold time CAS Latency=3 CLK high pulse width CAS Latency=2 CAS Latency=3 CLK low pulse width ...

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... K4S643232H SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self refresh Exit Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable ...

Page 13

... K4S643232H MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address / Function RFU RFU W.B.L Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 1 Reserved Write Burst Length A Length 9 0 Burst 1 Single Bit POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ...

Page 14

... K4S643232H BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address Sequential Sequential SDRAM Interleave Interleave Rev. 1.2 April 2006 ...

Page 15

... Device Operation & Timing Diagram DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...

Page 16

... Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t ...

Page 17

... SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. ...

Page 18

... DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out. 2) Clock Suspended During Read (BL=4) RD Masked by CKE Not Written 2) Read Mask (BL=4) RD Masked byDQM Note 2 Hi-Z Hi Hi-Z Hi x32 SDRAM Masked by CKE Suspended Dout Masked by DQM Hi Hi ...

Page 19

... By " Interrupt" meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write CAS to CAS delay. (=1CLK) CCD Last data in to new column address delay. (=1CLK) CDL Write interrupted by Read (BL=2) WR tCCD A DQ(CL2 DQ(CL3 tCDL Note x32 SDRAM RD Note Rev. 1.2 April 2006 ...

Page 20

... DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iii) CMD DQM DQ RD iv) CMD DQM DQ *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out Note Hi Hi Note x32 SDRAM D 3 Rev. 1.2 April 2006 ...

Page 21

... From the next generation, tRDL will be only 2CLK for every clock frequency Note 3,4 PRE Note Masked by DQM 2) Normal Read (BL=4) CLK PRE CMD DQ(CL2) tRDL Note 1,4 DQ(CL3) 2) Normal Read (BL=4) CLK CMD D 3 DQ(CL2) Note 3,4 DQ(CL3) Auto Precharge Starts from this point x32 SDRAM Note 2 RD PRE ...

Page 22

... From the next generation, tRDL will be only 2CLK for every clock frequency 2) Write Burst Stop (BL=8) PRE tRDL Note 1,5 4) Read Burst Stop (BL=4) PRE Note 3 1 DQ(CL2 DQ(CL3 MRS ACT tRP 2CLK - 22 x32 SDRAM CLK WR CMD STOP DQM tBDL CLK CMD RD STOP Rev ...

Page 23

... CKE *Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During t from auto refresh command, any other command can not be accepted. ...

Page 24

... See the BURST SEQUENCE TABLE. (BL= BL= BL=1, 2 Interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. At MRS A = "000". 2,1,0 At auto precharge, t should not be violated. ...

Page 25

... X BA RA, RA ILLEGAL ILLEGAL NOP (Continue Burst to End --> Precharge NOP (Continue Burst to End --> Precharge ILLEGAL X BA CA, A /AP ILLEGAL RA, RA ILLEGAL ILLEGAL NOP --> Idle after NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL /AP NOP --> Idle after x32 SDRAM ACTION Note Rev. 1.2 April 2006 ...

Page 26

... X X ILLEGAL NOP --> Idle after NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after 2 clocks NOP --> Idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address AP = Auto Precharge - 26 x32 SDRAM ACTION RCD RCD RFC RFC /AP). 10 Rev. 1.2 April 2006 Note ...

Page 27

... must be satisfied before any command other than exit x32 SDRAM ACTION INVALID Exit Self Refresh --> Idle after t (ABI) RFC Exit Self Refresh --> Idle after t (ABI) RFC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ...

Page 28

... HIGH tRAS tRC tSH tSS tCCD Cb Cc *Note 2,3 *Note 2,3 *Note *Note 3 *Note 3 tSH tSAC Qa Db tSLZ tSS tOH tSH tSS tSS tSH Write Read - 28 x32 SDRAM tRP Rb *Note *Note Row Active Precharge Rev. 1.2 April 2006 : Don't care ...

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