HYB39S256800DE-7.5 Infineon Technologies, HYB39S256800DE-7.5 Datasheet - Page 6

• Manufacturer Part Number: HYB39S256800DE-7.5
• Manufacturer: Infineon Technologies
• Type: SDRAMr

Specifications of HYB39S256800DE-7.5

• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

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Table 1
Part Number Speed Code
Speed Grade
max. Clock Frequency
1.2
The HYB39S256[40/80/16]0D[C/T](L) are four bank Synchronous DRAM’s organized as 4 banks x 16 MBit x4,
4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data
transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm
256-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically
and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge
of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher
rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst
length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V
power supply. All 256-Mbit components are available in P–TSOPII–54 and P–TFBGA–54 packages.
Data Sheet
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V
LVTTL Interface versions
Plastic Packages: P–TSOPII–54 400mil width (x4, x8, x16)
Chipsize Packages: P–TFBGA–54 (12 mm x 8 mm)
Overview
Features
Performance
Description
±
0.3 V Power Supply
@CL3
@CL2
f
t
t
t
t
CK3
CK3
AC3
CK2
AC2
–6
PC166 3–3–3
166
6
5
7.5
5.4
6
–7
PC133 2–2–2
143
7
5.4
7.5
5.4
HYB39S256[40/80/16]0D[C/T](L)
-7.5
PC133 3–3–3
133
7.5
5.4
10
6
256-MBit Synchronous DRAM
10072003-13LE-FGQQ
–8
PC100 2–2–2
125
8
6
10
6
Rev. 1.02, 2004-02
Overview
±
Unit
—
MHz
ns
ns
ns
ns
0.3 V