HYB39S256800DE-7.5 Infineon Technologies, HYB39S256800DE-7.5 Datasheet - Page 8

• Manufacturer Part Number: HYB39S256800DE-7.5
• Manufacturer: Infineon Technologies
• Type: SDRAMr

Specifications of HYB39S256800DE-7.5

• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

2
2.1
Table 3
Pin
CLK
CKE
CS
RAS
CAS
WE
A0 - A12
BA0, BA1 Input
DQx
DQM
LDQM
UDQM
Data Sheet
Type
Input
Input
Input
Input
Input
Input
Output
Input
Pin Configuration
Signal Pin Description
Signal Pin Description
Signal Polarity Function
Pulse
Level
Pulse
Pulse
Level
Level
Level
Pulse
Positive
Edge
Active
High
Active
Low
Active
Low
–
–
–
Active
High
Clock Input
The system clock input. All of the SDRAM inputs are sampled on the rising
edge of the clock.
Clock Enable
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby initiating either the Power Down mode, Suspend mode, or the
Self Refresh mode.
Chip Select
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
Command Signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
Address Inputs
During a Bank Activate command cycle, A0-A12 define the row address
(RA0-RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An define the column address
(CA0-CAn) when sampled at the rising clock edge. CAn depends upon the
SDRAM organization:
64M x4
32M x8
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10 (= AP) is used to invoke the
autoprecharge operation at the end of the burst read or write cycle. If A10
is high, autoprecharge is selected and BA0, BA1 defines the bank to be
precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all
four banks will be precharged regardless of the state of BA0 and BA1. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
Bank Select
Bank Select Inputs. Bank address inputs selects which of the four banks a
command applies to.
Data Input/Output
Data Input/Output pins operate in the same manner as on EDO or FPM
DRAMs.
Data Mask
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write mode,
DQM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM and UDQM
controls the lower and upper bytes in x16 SDRAMs.
SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
SDRAM CAn = CA9 (Page Length = 1024 bits)
8
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
10072003-13LE-FGQQ
Rev. 1.02, 2004-02
Pin Configuration