HYB39S256800DEL-7

Manufacturer Part NumberHYB39S256800DEL-7
ManufacturerInfineon Technologies
TypeSDRAM
HYB39S256800DEL-7 datasheet
 

Specifications of HYB39S256800DEL-7

Organization32Mx8Density256Mb
Address Bus15bAccess Time (max)5.4ns
Maximum Clock Rate143MHzOperating Supply Voltage (typ)3.3V
Package TypeTSOP-IIOperating Temp Range0C to 70C
Operating Supply Voltage (max)3.6VOperating Supply Voltage (min)3V
Supply Current90mAPin Count54
MountingSurface MountOperating Temperature ClassificationCommercial
Lead Free Status / Rohs StatusCompliant  
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HYB39S256800DEL-7 Summary of contents

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    ... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...

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    HYB39S256[40/80/16]0D[C/T](L) Revision History: Rev. 1.02 Page Subjects (major changes since last revision) 17 Corrected Mode Register Definition in chapter 3 all Various layout and editorial changes Previous Version: Rev. 1.01 all Various layout and editorial changes Previous Version: Rev. 1.0 ...

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    ... Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5.1 Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5.2 DQM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.3 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.4 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data Sheet HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM 5 Page Rev. 1.02, 2004-02 ...

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    ... Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. ...

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    ... P-TSOP-54-2 (400mil) 143MHz SDRAM P-TSOP-54-2 (400mil) 133MHz SDRAM P-TSOP-54-2 (400mil) 125MHz SDRAM P-TSOP-54-2 (400mil 16M x 4 SDRAM Low Power Versions (on request) P-TSOP-54-2 (400mil SDRAM Low Power Versions (on request) P-TSOP-54-2 (400mil SDRAM Low Power Versions (on request) P-TFBGA-54 (on request) 7 Overview Rev. 1.02, 2004-02 ...

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    ... High UDQM Data Sheet Clock Input The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Clock Enable Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiating either the Power Down mode, Suspend mode, or the Self Refresh mode ...

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    ... BA0 20 35 BA1 BA1 21 34 A10/AP A10/ TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch) 9 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Pin Configuration N.C. DQ7 DQ15 SSQ SSQ SSQ N.C. N.C. DQ14 DQ3 DQ6 DQ13 DDQ DDQ DDQ N.C. N.C. DQ12 N.C. DQ5 DQ11 V ...

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    ... A4 SS Table 6 Pin Configuration for x4 devices SSQ NC DQ3 V DDQ SSQ NC DQ2 V DDQ DQM CLK CKE A12 A11 Data Sheet HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM DDQ B V SSQ C V DDQ D V SSQ CAS G BA0 DDQ B V SSQ C V DDQ D V SSQ CAS G BA0 ...

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    ... Block Diagrams rray ffe r Figure 2 Block Diagram for 64M x 4 SDRAM (13/11/2 addressing) Data Sheet ffe ffe rray A rra ffe HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Pin Configuration R e fre rra tro & Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    ... Column Address Counter Row Decoder Memory Array Bank 0 8192 x 1024 x 8 Bit Input Buffer Figure 3 Block Diagram for 32M x 8 SDRAM (13/10/2 addressing) Data Sheet Column Addresses Row Addresses A0 - A9, AP A12, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Buffer ...

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    ... Column Address Counter Row Decoder Memory Array Bank 0 8192 x 512 x 16 Bit Input Buffer Figure 4 Block Diagram for 16M x 16 SDRAM (13/9/2 addressing) Data Sheet Column Addresses Row Addresses A0 - A8, AP A12, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Buffer ...

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    ... Functional Description 3.1 Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Table 7 Truth Table: Operation Command Operation Device State ...

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    ... Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During V V ...

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    ... Operating [13:7] w Operating Mode Mode Note: All other bit combinations are RESERVED. 0 burst read/burst write 1 burst read/single write Data Sheet (BA[1: MODE w for internal address sequence of low order address bits. 16 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Functional Description Rev. 1.02, 2004-02 10072003-13LE-FGQQ A0 ...

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    ... Commands Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes ...

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    ... RAS timing used to define either a read ( write ( this stage. SDRAM provides a wide variety of fast access modes single CAS cycle, serial data read or write operations are allowed 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i ...

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    ... In other words, unlike burst lengths and 8, fulll page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAMs, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum number of random column accesses ...

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    ... DDQ Operating Temperature Storage temperature range Power dissipation per SDRAM component Data out current (short circuit) Attention: Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability ...

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    ... Auto Refresh command cycling Self Refresh Current (standard components) t Self Refresh Mode, CKE=0.2V, Self Refresh Current (low power components) t Self Refresh Mode, CKE=0.2V, Data Sheet 1) =infinity CK =infinity CK 21 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Electrical Characteristics 2) Symbol Values min. max. C 2.5 3 2.5 3 ...

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    ... V = 3.3 V ± 0.3 V DDQ = 7.8 µs “distributed refresh”. 22 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Electrical Characteristics -8 Unit Note/ Test Condition 2) 2) 160 1.5 mA 0.85 mA Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    ... — 67 — RFC t 16 — 15 — RRD t 1 — 1 — CCD 23 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Electrical Characteristics –7 –6 Unit Notes PC166 - PC166 - 222 333 . 7 — 6 — ns 7.5 — 7.5 — ns — 143 — 166 MHz — 100 — ...

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    ... All AC measurements assume and parameters are measured with only, without any resistive termination 0.5) ns has to be added to this parameter has to be added to this parameter. 24 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Electrical Characteristics 1)2)3) –7 –6 Unit Notes PC166 - PC166 - 222 333 . – 64 – 64 ...

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    ... Figure 5 Measurement conditions for Data Sheet 1 Measurement conditions for IO.vsd and HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Electrical Characteristics and OH Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    ... Figure 6 Package Outline P–TSOPII–54 Data Sheet 15˚ ±5˚ 15˚ ±5˚ 0.1 54x 26x 0.8 = 20.8 0.2 54x 2.5 max 1) 22.22 ±0.13 26 HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM Package Outlines 2) 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 GPX09039 Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    ... TFBGA-54 package ( mm, 54 balls) Figure 7 Package Outline TFBGA-54 Data Sheet HYB39S256[40/80/16]0D[C/T](L) 256-MBit Synchronous DRAM 27 Package Outlines Rev. 1.02, 2004-02 10072003-13LE-FGQQ ...

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    ... Published by Infineon Technologies AG ...