HYB39S256800DEL-7 Infineon Technologies, HYB39S256800DEL-7 Datasheet - Page 17

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HYB39S256800DEL-7

Manufacturer Part Number
HYB39S256800DEL-7
Description
Manufacturer
Infineon Technologies
Type
SDRAMr
Datasheet

Specifications of HYB39S256800DEL-7

Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
90mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
3.3.1
Table 8
Burst Length
Note:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access withinthe
4. Whenever a boundary of the block is reached within a given sequence above, the following access wrapswithin
3.4
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS
refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip
address counter increments the word and the bank addresses and no bank information is required for both refresh
modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at aclock
timing. The mode restores word line after the refresh and no external precharge command is necessary.
Aminimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies
toany access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock
aredisabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit
command,at least one
Data Sheet
2
4
8
FullPage
block.
block.
the block.
Burst Length
Burst Length and Sequence
Commands
Starting Column Address
A2
0
0
0
0
1
1
1
1
n
t
RC
delay is required prior to any access command.
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Order of Accesses within a Burst
Type=Sequential
0–1
1–0
0–1–2–3
1–2–3–0
2–3–0–1
3–0–1–2
0–1–2–3–4–5–6–7
1–2–3–4–5–6–7–0
2–3–4–5–6–7–0–1
3–4–5–6–7–0–1–2
4–5–6–7–0–1–2–3
5–6–7–0–1–2–3–4
6–7–0–1–2–3–4–5
7–0–1–2–3–4–5–6
Cn, Cn+1, Cn+2 ....
17
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Type=Interleaved
0–1
1–0
0–1–2–3
1–0–3–2
2–3–0–1
3–2–1–0
0–1–2–3–4–5–6–7
1–0–3–2–5–4–7–6
2–3–0–1–6–7–4–5
3–2–1–0–7–6–5–4
4–5–6–7–0–1–2–3
5–4–7–6–1–0–3–2
6–7–4–5–2–3–0–1
7–6–5–4–3–2–1–0
not supported
Functional Description
10072003-13LE-FGQQ
Rev. 1.02, 2004-02

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