HYB39S256800DEL-7.5 Infineon Technologies, HYB39S256800DEL-7.5 Datasheet - Page 15

• Manufacturer Part Number: HYB39S256800DEL-7.5
• Manufacturer: Infineon Technologies
• Type: SDRAMr

Specifications of HYB39S256800DEL-7.5

• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

3.2
The default power on state of the mode register is supplier specific and may be undefined. The following power
on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a
conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During
power on, all
are held in the “NOP” state. The power on voltage must not exceed
supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 ms is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all
banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A
minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming
the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
3.3
The Mode register designates the operation mode at the read or write cycle. This register is divided into four fields.
First, a Burst Length Field which sets the length of the burst, Second, an Addressing Selection bit which programs
the column access sequence in a burst cycle (interleaved or sequential). Third, a CAS Latency Field to set the
access time at clock cycle. Fourth, an Operation mode field to differentiate between normal operation (Burst read
and burst Write) and a special Burst Read and Single Write mode. After the initial power up, the mode set
operation must be done before any activate command. Any content of the mode register can be altered by re-
executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock
before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals
of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Data Sheet
Initialization
Mode Register Definition
V
DD
and
V
DDQ
pins must be built up simultaneously to the specified voltage when the input signals
15
V
DD
HYB39S256[40/80/16]0D[C/T](L)
+0.3V on any of the input pins or
256-MBit Synchronous DRAM
Functional Description
10072003-13LE-FGQQ
Rev. 1.02, 2004-02
V
DD