HYB39S256800DEL-7.5 Infineon Technologies, HYB39S256800DEL-7.5 Datasheet - Page 18

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HYB39S256800DEL-7.5

Manufacturer Part Number
HYB39S256800DEL-7.5
Description
Manufacturer
Infineon Technologies
Type
SDRAMr
Datasheet

Specifications of HYB39S256800DEL-7.5

Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
90mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one
extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a
Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the
precharge operation a time delay equal to
Auto-Precharge may only be interrupted by a burst start to another bank. It must not be interrupted by a precharge
or a burst stop command.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock
timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as
shown in the following list. The precharge command can be imposed one clock before the last data out for CAS
latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr (“write
recovery time”) of 2 clocks minimum from the last data out to apply the precharge command.
Table 9
A10
0
0
0
0
1
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst
operation prematurely. These methods include using another Read or Write Command to interrupt an existing
burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst
Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command
care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions
making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be
ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the
memory.
3.5
3.5.1
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According
to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline
are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay,
from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations
are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the
mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column addresses are segmented by the burst length
and serial data accesses are done within this boundary. The first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and
its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest
of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Data Sheet
Bank Selection by Address Bits
Operations
Read and Write
BA0
0
0
1
1
1
BA1
0
1
0
1
X
t
WR
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
(“write recovery time”) after the last data in. A burst operation with
18
HYB39S256[40/80/16]0D[C/T](L)
256-MBit Synchronous DRAM
Functional Description
10072003-13LE-FGQQ
Rev. 1.02, 2004-02
t
RCD

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