DS31415DK Maxim Integrated Products, DS31415DK Datasheet

DS31415DK

Manufacturer Part Number

DS31415DK

Description

Clock & Timer Development Tools DS31415 Dev Kit

Manufacturer

Maxim Integrated Products

Datasheet

1.DS31415DK.pdf (5 pages)

Specifications of DS31415DK

Lead Free Status / Rohs Status

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The DS31415 is a flexible, high-performance timing IC

for

synthesis applications. On each of its three input clocks

and four output clocks, the device can accept or

generate nearly any frequency between 2kHz and

750MHz.

The input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for the

rest of the device. A flexible, high-performance digital

PLL locks to the selected reference and provides

programmable bandwidth, very high resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLL is followed by a clock synthesis

subsystem that has two fully programmable digital

frequency synthesis blocks, a high-speed low-jitter

APLL, and four output clocks, each with its own 32-bit

divider and phase adjustment. The APLL provides

fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31415 has all required

features and functions to serve as a central timing

function or as a line card timing IC.

In addition the DS31415 has an embedded IEEE 1588

clock that can be steered by system software to follow a

time master elsewhere in the system or elsewhere in

the network. This clock has all necessary features to be

the central time clock in a 1588 ordinary clock,

boundary clock or transparent clock.

Frequency Conversion and IEEE1588 Time/Frequency

Telecom Line Cards or Timing Cards with Any Mix of

+Denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of

any device may be simultaneously available through various sales channels. For information about device errata, go to:

www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or

visit Maxim’s website at www.maxim-ic.com.

19-5712; Rev 1; 3/11

DS31415GN+

Applications in a Wide Variety of Equipment Types

SONET/SDH, Synchronous Ethernet and/or OTN

Ports in WAN Equipment Including MSPPs, Ethernet

Switches, Routers, DSLAMs, and Base Stations

diverse

PART

frequency

-40C to +85C

TEMP RANGE

Ordering Information

with Sub-ps Output Jitter and 1588 Clock

General Description

3-Input, 4-Output, Single DPLL Timing IC

conversion

ABRIDGED DATA SHEET

Applications

and

PIN-PACKAGE

256 CSBGA

frequency



Three Input Clocks

High-Performance DPLL

Two Digital Frequency Synthesizers

High-Performance Output APLL

Four Output Clocks in Two Groups

IEEE 1588 Clock Features

General Features



Differential or CMOS/TTL Format

Any Frequency from 2kHz to 750MHz

Fractional Scaling for 64B/66B and FEC Scaling

(e.g., 64/66, 237/255, 238/255) or Any Other

Downscaling Requirement

Continuous Input Clock Quality Monitoring

Three 2/4/8kHz Frame Sync Inputs

Hitless Reference Switching on Loss of Input

Automatic or Manual Phase Build-Out

Holdover on Loss of All Inputs

Programmable Bandwidth, 0.5mHz to 400Hz

Produce Any 2kHz Multiple Up to 77.76MHz

Per-DFS Phase Adjustment

Output Frequencies to 750MHz

High Resolution Fractional Scaling for FEC and

64B/66B (e.g., 255/237, 255/238, 66/64) or Any

Other Scaling Requirement

Less than 1ps RMS Output Jitter

Nearly Any Frequency from < 1Hz to 750MHz

Each Group Slaves to a DFS Clock, Any APLL

Clock, or Any Input Clock (Divided and Scaled)

Each Has a Differential Output (3 CML, 4 LVDS/

LVPECL

32-Bit Frequency Divider Per Output

Two Sync Pulse Outputs: 8kHz and 2kHz

Steerable by Software with 2

Resolution and 2

4ns Input Timestamp Accuracy and Output

Edge Placement Accuracy

Programmable Clock and Time-Alignment I/O to

Synchronize All 1588 Devices in Large Systems

Supports 1588 OC, BC, and TC Architectures

Suitable Line Card IC or Timing Card IC for

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

Accepts and Produces Nearly Any Frequency

from 1Hz Up to 750MHz

Internal Compensation for Local Oscillator Frequency Error

SPI™ Processor Interface

1.8V Operation with 3.3V I/O (5V Tolerant)

)

and Separate CMOS/TTL Output

-32

Maxim Integrated Products 1

ns Frequency Resolution

DS31415

-8

ns Time

Features

Related parts for DS31415DK

DS31415DK Summary of contents

Page 1

... Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU  Accepts and Produces Nearly Any Frequency from 1Hz Up to 750MHz  Internal Compensation for Local Oscillator Frequency Error  SPI™ Processor Interface  1.8V Operation with 3.3V I/O (5V Tolerant) Maxim Integrated Products 1 ...

Page 2

ABRIDGED DATA SHEET Application Example Typical Application Example, Traditional Frequency Synchronization Typical Application Example, Frequency and Time Synchronization from port cards, for SyncE or 1588+SyncE operation Processor 1588 Software Local OSC TCXO or SPI OCXO DS31415 1588 system time, e.g. ...

Page 3

ABRIDGED DATA SHEET Block Diagram DS31415 SYNC1 SYNC2 SYNC3 Input Clock Block IC1 POS/NEG 3 IC2 POS/NEG Frequency Scaler, Activity Monitor, IC3 POS/NEG Freq. Monitor, Clock Optional Inversion status (per input clock) Selector JTRST JTMS JTAG JTCLK JTDI JTDO MFSYNC ...

Page 4

ABRIDGED DATA SHEET Detailed Features Input Clock Features  Three input clocks, differential or CMOS/TTL signal format  Input clocks can be any frequency from 2kHz up to 750MHz  Per-input fractional scaling (i.e., multiplying by ND where N is ...

Page 5

ABRIDGED DATA SHEET Output Clock Features  Four output clock signals in two groups  Output clock group OC1 has a very high-speed differential output (current-mode logic, separate CMOS/TTL output (≤ 125MHz)  Output clock group OC4 has a high-speed ...

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