MT29F2G08ABAEAWP:E Micron Technology Inc, MT29F2G08ABAEAWP:E Datasheet
MT29F2G08ABAEAWP:E
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MT29F2G08ABAEAWP:E Summary of contents
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NAND Flash Memory MT29F2G08ABAEAH4, MT29F2G08ABAEAWP, MT29F2G08ABBEAH4 MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4 MT29F2G16ABBEAHC Features • Open NAND Flash Interface (ONFI) 1.0-compliant • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 ...
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Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for ...
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Contents General Description ......................................................................................................................................... 8 Signal Descriptions .......................................................................................................................................... 8 Signal Assignments ........................................................................................................................................... 9 Package Dimensions ...................................................................................................................................... 12 Architecture ................................................................................................................................................... 15 Device and Array Organization ....................................................................................................................... 16 Asynchronous Interface Bus Operation ........................................................................................................... 18 Asynchronous Enable/Standby ................................................................................................................... 18 Asynchronous Commands .......................................................................................................................... 18 ...
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READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................ 73 PROGRAM FOR INTERNAL DATA MOVE (85h–10h) .................................................................................... 74 PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................ 75 Block Lock Feature ......................................................................................................................................... 76 WP# and Block Lock ................................................................................................................................... 76 UNLOCK (23h-24h) .................................................................................................................................... 76 ...
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List of Tables Table 1: Signal Definitions ............................................................................................................................... 8 Table 2: Array Addressing – MT29F2G08 (x8) .................................................................................................. 16 Table 3: Array Addressing – MT29F2G16 (x16) ................................................................................................ 17 Table 4: Asynchronous Interface Mode Selection ........................................................................................... 18 Table 5: Command Set .................................................................................................................................. ...
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List of Figures Figure 1: Marketing Part Number Chart ........................................................................................................... 2 Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ............................................................................................... 9 Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ....................................................................................... 10 Figure 4: 63-Ball VFBGA, x16 (Balls ...
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Figure 51: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ........... 74 Figure 52: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ....................................................... 74 Figure 53: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) ...
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General Description Micron NAND Flash devices include an asynchronous data interface for high-perform- ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the ...
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Signal Assignments Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) x16 R/B# R/B# RE# RE# CE# CE Vcc Vcc Vss Vss ...
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Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View For the 3V device, G5 changes to DNU. NO LOCK function is available ...
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Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View For the 3V device, G5 changes to DNU. NO LOCK function is available ...
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Package Dimensions Figure 5: 48-Pin TSOP – Type 1, CPL 1 12.00 ±0.08 24 +0.03 0.15 -0.02 1. All dimensions are in millimeters. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory 20.00 ±0.25 ...
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Figure 6: 63-Ball VFBGA (10.5mm x 13mm) Seating plane A 0.12 A 63X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply solder balls post- reflow on Ø0.4 SMD ball pads. 8.8 ...
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Figure 7: 63-Ball VFBGA (9mm x 11mm) Seating plane A 0.12 A 63X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post reflow on Ø0.4 SMD ball pads. 8.8 CTR 0.8 TYP 1. All ...
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Architecture These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register ...
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Device and Array Organization Figure 9: Array Organization – MT29F2G08 (x8) Cache Register 2048 Data Register 2048 1024 blocks 1 block per plane 2048 blocks per device Plane of even-numbered blocks ( ..., 2044, 2046) Table 2: ...
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Figure 10: Array Organization – MT29F2G16 (x16) Cache Register 1024 Data Register 1024 1024 blocks per plane 1 block 2048 blocks per device Plane of even-numbered blocks ( ..., 2044, 2046) Table 3: Array Addressing – MT29F2G16 ...
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Asynchronous Interface Bus Operation The bus on the device is multiplexed. Data I/O, addresses, and commands all share the same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and com- mands are always supplied on I/O[7:0]. ...
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Figure 11: Asynchronous Command Latch Cycle CLE CE# WE# ALE I/Ox PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Bus Operation t t CLS CLH ...
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Asynchronous Addresses An asynchronous address is written from I/O[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH. Bits that are not part of the ...
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Asynchronous Data Input Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH. Data input is ...
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Asynchronous Data Output Data can be output from a die (LUN READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the ...
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Figure 15: Asynchronous Data Output Cycles (EDO Mode) CE# RE# t CEA I/ RDY Write Protect# The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE ...
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R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller. The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The ...
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Figure 17: Fall and Rise (3.3V V 3.50 3.00 2.50 2.00 V 1.50 1.00 0.50 0. Fall and Notes Rise dependent on external capacitance and resistive loading and output transistor im- pedance ...
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Figure 19 (mA) Figure 20: I vs. Rp (1. (mA) PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN Asynchronous Interface Bus Operation ) CC 3.50 3.00 ...
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Figure 21: TC vs. Rp T(ns) PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN Asynchronous Interface Bus Operation 1200 1000 800 600 400 200 0 0 2000 4000 27 Micron Technology, Inc. reserves the right to change products or specifications ...
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Device Initialization Micron NAND Flash devices are designed to prevent data corruption during power tran- sitions. V protection during power transitions.) When ramping V to initialize the device: 1. Ramp V 2. The host must wait for R/ ...
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Command Definitions Table 5: Command Set Command Command Cycle #1 Reset Operations RESET FFh Identification Operation READ ID 90h READ PARAMETER PAGE ECh READ UNIQUE ID EDh Feature Operations GET FEATURES EEh SET FEATURES EFh Status Operations READ STATUS 70h ...
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Table 5: Command Set (Continued) Command Command Cycle #1 Block Lock Operations BLOCK UNLOCK LOW 23h BLOCK UNLOCK HIGH 24h BLOCK LOCK 2Ah BLOCK LOCK-TIGHT 2Ch BLOCK LOCK READ 7Ah STATUS One-Time Programmable (OTP) Operations OTP DATA LOCK BY 80h ...
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Table 6: Two-Plane Command Set (Continued) Note 4 applies to all parameters and conditions Com- mand Command Cycle #1 PROGRAM PAGE 80h TWO-PLANE PROGRAM PAGE 80h CACHE MODE TWO- PLANE PROGRAM FOR TWO- 85h PLANE INTERNAL DA- TA MOVE BLOCK ...
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Reset Operations RESET (FFh) The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the ...
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Identification Operations READ ID (90h) The READ ID (90h) command is used to read identifier codes programmed into the tar- get. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing 90h ...
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READ ID Parameter Tables Table 7: READ ID Parameters for Address 00h Options Byte 0 – Manufacturer ID Manufacturer Micron Byte 1 – Device ID MT29F2G08ABBEA 2Gb, x8, 1.8V MT29F2G16ABBEA 2Gb, x16, 1.8V MT29F2G08ABAEA 2Gb, x8, 3.3V MT29F2G16ABAEA 2Gb, x16, ...
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Table 7: READ ID Parameters for Address 00h (Continued) Options Internal ECC ECC disabled ECC enabled Byte value MT29F2G08ABBEA MT29F2G16ABBEA MT29F2G08ABAEA MT29F2G16ABAEA binary hexadecimal. Note: Table 8: READ ID Parameters for Address 20h Byte Options ...
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READ PARAMETER PAGE (ECh) The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing ...
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Parameter Page Data Structure Tables Table 9: Parameter Page Data Structure Byte Description 0–3 Parameter page signature 4–5 Revision number 6–7 Features supported 8–9 Optional commands supported 10–31 Reserved 32–43 Device manufacturer PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN ...
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Table 9: Parameter Page Data Structure (Continued) Byte Description 44–63 Device model 64 Manufacturer ID 65–66 Date code 67–79 Reserved 80–83 Number of data bytes per page 84–85 Number of spare bytes per page 86–89 Number of data bytes per ...
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Table 9: Parameter Page Data Structure (Continued) Byte Description 112 Number of bits ECC bits 113 Number of interleaved address bits 114 Interleaved operation attributes 115–127 Reserved 128 I/O pin capacitance 129–130 Timing mode support 131–132 Program cache timing mode ...
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Table 9: Parameter Page Data Structure (Continued) Byte Description 166–253 Vendor-specific 254–255 Integrity CRC 256–511 Value of bytes 0–255 512–767 Value of bytes 0–255 768+ Additional redundant parameter pages hexadecimal. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H ...
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READ UNIQUE ID (EDh) The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EDh ...
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Feature Operations The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which subfeature parameters will be read or modified. Each feature address ...
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Table 11: Feature Address 90h – Array Operation Mode Subfeature Parameter Options 1/O7 P1 Operation Normal mode option OTP operation OTP protection Disable ECC Enable ECC P2 Reserved P3 Reserved P4 Reserved Note: 1. These bits are reset to 00h ...
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GET FEATURES (EEh) The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EEh to the command ...
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Table 12: Feature Addresses 01h: Timing Mode Subfeature Parameter Options P1 Timing mode Mode 0 (default) Mode 1 Mode 2 Mode 3 Mode 4 Mode The timing mode feature address is used to change the ...
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Table 13: Feature Addresses 80h: Programmable I/O Drive Strength Subfeature Parameter Options P1 I/O drive strength Full (default) Three-quarters One-half One-quarter The programmable drive strength feature address is used to change the default I/O Note: drive ...
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Status Operations Each die (LUN) provides its status independently of other die (LUNs) on the same tar- get through its 8-bit status register. After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued, status register output is ...
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READ STATUS (70h) The READ STATUS (70h) command returns the status of the last-selected die (LUN target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0). If there is only ...
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Figure 31: READ STATUS ENHANCED (78h) Operation Cycle type I/Ox PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Command Address Address Address t WHR 78h Micron Technology, Inc. reserves the ...
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Column Address Operations The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for man- aging data, especially when the host internal buffer is ...
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RANDOM DATA READ TWO-PLANE (06h-E0h) The RANDOM DATA READ TWO-PLANE (06h-E0h) command enables data output on the addressed die’s (LUN’s) cache register at the specified column address. This com- mand is accepted by a die (LUN) when it is ready ...
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RANDOM DATA INPUT (85h) The RANDOM DATA INPUT (85h) command changes the column address of the selec- ted cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it ...
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PROGRAM FOR INTERNAL DATA INPUT (85h) The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address ...
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Figure 35: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation As defined for PAGE (CACHE) PROGRAM Cycle type I/O[7: RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN Command Address Address Address Address ...
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Read Operations The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register. During data output the following commands can be used ...
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Two-Plane Read Operations Two-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. This is done by prepend- ing one or more READ PAGE TWO-PLANE (00h-00h-30h) commands in front ...
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For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, t RCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh). When RDY = 1 ...
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READ PAGE (00h-30h) com- mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enable data output in the other cache registers. Figure 36: READ PAGE (00h-30h) Operation Cycle ...
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Figure 38: READ PAGE CACHE SEQUENTIAL (31h) Operation Cycle type Command Address x5 Command I/O[7:0] 00h Page Address M 30h t WB RDY READ PAGE CACHE RANDOM (00h-31h) The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and ...
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Figure 39: READ PAGE CACHE RANDOM (00h-31h) Operation Cycle type Command Address x5 Command 00h Page Address M 30h I/O[7:0] RDY Cycle type D Command Address x5 OUT I/O[7:0] Dn 00h Page Address P RDY 1 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – ...
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READ PAGE CACHE LAST (3Fh) The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it ...
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READ PAGE TWO-PLANE 00h-00h-30h The READ PAGE TWO-PLANE (00h-00h-30h) operation is similar to the PAGE READ (00h-30h) operation. It transfers two pages of data from the NAND Flash array to the data registers. Each page must be from a different ...
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Figure 41: READ PAGE TWO-PLANE (00h-00h-30h) Operation CLE WE# ALE RE# Page address M Col Col 00h I/Ox add 1 add 2 Column address J R/B# CLE WE# ALE RE# I/ OUT OUT Plane 0 data ...
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Program Operations Program operations are used to move data from the cache or data registers to the NAND array. During a program operation the contents of the cache and/or data regis- ters are modified by the internal control logic. Within ...
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PROGRAM PAGE (80h-10h) The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page ad- dress in the array of the selected ...
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PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1 also accepted by the die ...
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Figure 43: PROGRAM PAGE CACHE (80h–15h) Operation (Start) Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY 1 Figure 44: PROGRAM PAGE CACHE (80h–15h) Operation (End) As defined for ...
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PROGRAM PAGE TWO-PLANE (80h-11h) The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the NAND Flash array. This command can be ...
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Figure 45: PROGRAM PAGE TWO-PLANE (80h–11h) Operation Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory D Address Address Address IN t ADL R1 R2 ...
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Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK TWO- ...
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ERASE BLOCK TWO-PLANE (60h-D1h) The ERASE BLOCK TWO-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address ...
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Internal Data Move Operations Internal data move operations make it possible to transfer data within a device from one page to another using the cache register. This is particularly useful for block man- agement and wear leveling. The INTERNAL DATA ...
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READ FOR INTERNAL DATA MOVE (00h-35h) The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command reg- ister instead of 30h. Though it is not ...
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Figure 50: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] 00h 35h (5 cycles) Source address Figure 51: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] ...
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Figure 53: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) Cycle type Command Address I/O[7:0] 85h RDY Cycle type Command I/O[7:0] 85h RDY 1 PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) The PROGRAM FOR INTERNAL DATA MOVE ...
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Block Lock Feature The block lock feature protects either the entire device or ranges of blocks from being programmed and erased. Using the block lock feature is preferable to using WP# to pre- vent PROGRAM and ERASE operations. Block lock ...
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Figure 55: Flash Array Protected: Invert Area Bit = 0 Block 2047 Block 2046 Block 2045 Block 2044 Block 2043 Block 2042 Block 2041 Block 2040 Block 2039 . . . . . . . . . . . . ...
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Table 16: Block Lock Address Cycle Assignments 1 ALE Cycle I/O[15:8] I/O7 First LOW BA7 Second LOW BA15 Third LOW LOW 1. I/O[15:8] is applicable only for x16 devices. Notes: 2. Invert area bit is applicable for 24h command; it ...
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LOCK (2Ah) By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UN- LOCK (23h) command, they can be locked again ...
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LOCK TIGHT (2Ch) The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and al- so prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an ...
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Figure 60: PROGRAM/ERASE Issued to Locked Block R/B# PROGRAM or ERASE I/Ox BLOCK LOCK READ STATUS (7Ah) The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The address cycles have the same ...
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Figure 62: BLOCK LOCK Flowchart Entire NAND Flash array locked tight Unlocked range WP# LOW >100ns or LOCK Cmd Locked range Unlocked range UNLOCK Cmd with invert area LOCK TIGHT Cmd bit = 1 with WP# and LOCK HIGH Unlocked ...
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One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on the device, and the entire range is guaranteed to ...
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OTP DATA PROGRAM (80h-10h) The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time page can be partially programmed up to ...
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RANDOM DATA INPUT (85h) After the initial OTP data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of ...
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Figure 64: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Opera- tion Mode) CLE CE WE# ALE RE# Col Col OTP I/Ox 00h 80h 1 add1 page add2 SERIAL DATA INPUT command R/B# OTP DATA ...
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Figure 65: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) CLE CE WE# ALE RE# Col I/Ox 80h 00h OTP DATA PROTECT command R/B# 1. OTP data is protected following a good status confirmation. Note: PDF: 09005aef83b83f42 ...
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OTP DATA READ (00h-30h) To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is ...
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Figure 67: OTP DATA READ with RANDOM DATA READ Operation CLE CE# WE# ALE RE# Col Col OTP I/Ox 00h add 1 add 2 page Column address n R/B# Note: 1. The OTP page must be within the range 02h–1Fh. ...
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Two-Plane Operations Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific ...
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Figure 68: TWO-PLANE PAGE READ CLE WE# ALE RE# Page address M Col Col 00h I/Ox add 1 add 2 Column address J R/B# CLE WE# ALE RE# I/ OUT OUT Plane 0 data R/B# 1 ...
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Figure 69: TWO-PLANE PAGE READ with RANDOM DATA READ R/B# RE# 00h Address (5 cycles) 00h I/Ox Plane 0 address R/B# RE# I/Ox 06h Address (5 cycles) E0h Plane 1 address 1 Figure 70: TWO-PLANE PROGRAM PAGE R/B# I/Ox 80h ...
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Figure 71: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT R/B# I/Ox 80h Address (5 cycles) Data 1st-plane address R/B# I/Ox 85h Address (2 cycles) Data Different column address than previous 1 5 address cycles, for 2nd plane only Unlimited number ...
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Figure 72: TWO-PLANE PROGRAM PAGE CACHE MODE R/B# 80h Address/data input I/Ox 1st plane R/B# 80h Address/data input I/Ox 1st plane 1 R/B# 80h Address/data input I/Ox 1st plane 2 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, ...
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Figure 73: TWO-PLANE INTERNAL DATA MOVE R/B# 00h Address (5 cycles) I/Ox 1st-plane source R/B# 85h Address (5 cycles) I/Ox 2nd-plane destination 1 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/ 00h Address (5 cycles) 35h 2nd-plane source ...
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Figure 74: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ R/B# RE# I/Ox 00h Address (5 cycles) 00h 1st-plane source R/B# RE# I/Ox Data output Data from 1 2nd-plane source R/B# RE# I/Ox 85h Address (5 cycles) 11h 1st-plane ...
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Figure 75: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT R/B# 00h 00h I/Ox Address (5 cycles) 1st-plane source t DBSY R/B# 85h I/Ox Address (5 cycles) 2nd-plane destination 1 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/ ...
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Figure 76: TWO-PLANE BLOCK ERASE CLE CE# WE# ALE R/B# RE# I/Ox Address input (3 cycles) 60h 1st plane Figure 77: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle CE# CLE WE# ALE RE# I/Ox 78h PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN ...
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Interleaved Die (Multi-LUN) Operations In devices that have more than one die (LUN) per target possible to improve per- formance by interleaving operations between the die (LUNs). An interleaved die (multi- LUN) operation is one that is issued ...
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Error Management Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An ...
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Table 18: Error Management Details (Continued) Description Minimum ECC with internal ECC enabled Minimum required ECC for block 0 if PROGRAM/ ERASE cycles are less than 1000 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash ...
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Internal ECC and Spare Area Mapping for ECC Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256 words (x16) of the main area and 4 bytes (x8 words (x16) of metadata I ...
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Figure 79: Spare Area Mapping (x16) Max word Min word ECC Protected Address Address 0FFh 000h Yes 1FFh 100h Yes 2FFh 200h Yes 3FFh 300h Yes 400h 400h No 401h 401h No 403h 402h Yes 407h 404h Yes 408h 408h ...
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Electrical Specifications Stresses greater than those listed can cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of ...
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Table 22: Capacitance Notes 1–2 apply to all parameters and conditions Description Input capacitance Input/output capacitance (I/O) 1. These parameters are verified in device characterization and are not 100% tested. Notes: 2. Test conditions: T Table 23: Test Conditions Parameter ...
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Electrical Specifications – DC Characteristics and Operating Conditions Table 24: DC Characteristics and Operating Conditions (3.3V) Parameter Conditions t t Sequential READ current (MIN); CE PROGRAM current ERASE current Standby current (TTL) WP# = 0V/V ...
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Table 25: DC Characteristics and Operating Conditions (1.8V) Parameter Conditions t t Sequential READ current (MIN); CE PROGRAM current ERASE current Standby current (TTL) WP# = 0V/V Standby current (CMOS) CE WP# = ...
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Electrical Specifications – AC Characteristics and Operating Conditions Table 26: AC Characteristics: Command, Data, and Address Input (3.3V) Note 1 applies to all Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time ...
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Table 28: AC Characteristics: Normal Operation (3.3V) Note 1 applies to all Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Output High-Z to RE# LOW READ ...
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Table 29: AC Characteristics: Normal Operation (1.8V) (Continued) Note 1 applies to all Parameter RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH ...
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Electrical Specifications – Program/Erase Characteristics Table 30: Program/Erase Characteristics Parameter Number of partial-page programs BLOCK ERASE operation time Busy time for PROGRAM CACHE operation Cache read busy time Busy time for SET FEATURES and GET FEATURES operations Busy time for ...
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Asynchronous Interface Timing Diagrams Figure 80: RESET Operation CLE CE WE# R/B# FFh I/O[7:0] RESET command Figure 81: READ STATUS Cycle CLE CE# WE# RE# I/O[7:0] PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND ...
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Figure 82: READ STATUS ENHANCED Cycle t CS CE# t CLS t CLH CLE t WP WE# ALE RE I/O[7:0] 78h Figure 83: READ PARAMETER PAGE CLE WE ALE RE# I/O[7:0] ECh 00h R/B# ...
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Figure 84: READ PAGE CLE CE WE# ALE RE# Col Col I/Ox 00h add 1 add 2 RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Timing Diagrams t WB ...
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Figure 85: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE RDY WE# I/Ox 00h Address (5 cycles) PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Timing Diagrams t t ...
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Figure 86: RANDOM DATA READ CLE CE# WE# ALE t RC RE RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN Asynchronous Interface Timing Diagrams t RHW Col Col D 05h OUT OUT add 1 ...
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Figure 87: READ PAGE CACHE SEQUENTIAL CLE t CLS t CLH CE WE# ALE RE Row Col Col I/Ox 00h add 1 add 2 add 1 Column address 00h RDY ...
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Figure 88: READ PAGE CACHE RANDOM CLE t CLS t CLH CE WE# ALE RE Col Col I/Ox 00h add 1 add 2 Column address 00h RDY CLE CE# WE# ...
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Figure 89: READ ID Operation CLE CE# WE# ALE RE# I/Ox 90h 00h or 20h Address, 1 cycle Figure 90: PROGRAM PAGE Operation CLE CE WE# ALE RE# Col Col I/Ox 80h add 1 add 2 RDY PDF: ...
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Figure 91: PROGRAM PAGE Operation with CE# “Don’t Care” CLE CE# WE# ALE I/Ox 80h Address (5 cycles) Figure 92: PROGRAM PAGE Operation with RANDOM DATA INPUT CLE CE WE# ALE RE# Col Col Row Row I/Ox 80h ...
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Figure 93: PROGRAM PAGE CACHE CLE CE WE# ALE RE# Row Row Row Col Col I/Ox 80h add 1 add 2 add 1 add 2 add 3 RDY Last page - 1 Figure 94: PROGRAM PAGE CACHE Ending ...
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Figure 95: INTERNAL DATA MOVE CLE CE WE# ALE RE# Col Col Row Row I/Ox 00h add 1 add 2 add 1 add 2 RDY Figure 96: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled t R_ECC R/B# ...
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Figure 97: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] 00h 35h 70h (5 cycles) Source address SR bit READ successful SR bit READ error ...
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Revision History Rev. H, Production – 9/10 • From preliminary to production status Rev. G, Preliminary – 8/10 • Corrected errors in bytes 44–63 in Parameter Page Data Structure Table Rev. F, Preliminary – 6/10 • Added block endurance info ...
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