ISL88731CEVAL2Z Intersil, ISL88731CEVAL2Z Datasheet - Page 13

• Manufacturer Part Number: ISL88731CEVAL2Z
• Description: ISL88731C EVALUATION BOARD 2 - 28 Ld TQFN - COMPLI
• Manufacturer: Intersil
• Series: -r

Specifications of ISL88731CEVAL2Z

• Main Purpose: Power Management, Battery Charger
• Embedded: No
• Utilized Ic / Part: ISL88731C
• Primary Attributes: Li-Ion / Li-Pol, SMBus interface
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

START
SDA
Acknowledge
Each address and data transmission uses 9-clock pulses. The ninth
pulse is the acknowledge bit (ACK). After the start condition, the
master sends 7-slave address bits and a R/W bit during the next
8-clock pulses. During the ninth clock pulse, the device that
recognizes its own address holds the data line low to acknowledge.
The acknowledge bit is also used by both the master and the slave
to acknowledge receipt of register addresses and data (see
Figure 20).
SMBus Transactions
All transactions start with a control byte sent from the SMBus master
device. The control byte begins with a Start condition, followed by 7-bits
of slave address (0001001 for the ISL88731C) followed by the R/W bit.
The R/W bit is 0 for a write or 1 for a read. If any slave devices on the
SMBus bus recognize their address, they will Acknowledge by pulling
the serial data (SDA) line low for the last clock cycle in the control byte. If
no slaves exist at that address or are not ready to communicate, the
data line will be 1, indicating a Not Acknowledge condition.
SCL
REGISTER
ADDRESS
0x14
0x15
0x3F
0xFE
0xFF
S
S
FIGURE 20. ACKNOWLEDGE ON THE I
MSB
Write To A Register
SLAVE
ADDR + W
Read From A Register
SLAVE
ADDR + W
S
P
1
START
STOP
REGISTER NAME
ManufacturerID
ChargeCurrent
ChargeVoltage
InputCurrent
DeviceID
2
13
A
A
REGISTER
REGISTER
FIGURE 21. SMBus/ISL88731C READ AND WRITE PROTOCOL
ADDR
ADDR
TABLE 1. BATTERY CHARGER REGISTER SUMMARY
8
2
C BUS
ACKNOWLEDGE
A
N
FROM SLAVE
Read or Write
Read or Write
Read or Write
READ/WRITE
A
A
Read Only
Read Only
ACKNOWLEDGE
NO ACKNOWLEDGE
9
P
ISL88731C
LO BYTE
DATA
S
SLAVE
ADDR + R
6-bit Charge Current Setting
11-bit Charge Voltage Setting
6-bit Charge Current Setting
Manufacturer ID
Device ID
Once the control byte is sent, and the ISL88731C acknowledges
it, the 2nd byte sent by the master must be a register address
byte such as 0x14 for the ChargeCurrent register. The register
address byte tells the ISL88731C which register the master will
write or read. See Table 1 for details of the registers. Once the
ISL88731C receives a register address byte it responds with an
acknowledge.
Byte Format
Every byte put on the SDA line must be eight bits long and must
be followed by an acknowledge bit. Data is transferred with the
most significant bit first (MSB) and the least significant bit last
(LSB).
ISL88731C and SMBus
The ISL88731C receives control inputs from the SMBus
interface. The serial interface complies with the SMBus protocols
as documented in the System Management Bus Specification
V1.1, which can be downloaded from www.smbus.org. The
ISL88731C uses the SMBus Read-Word and Write-Word
protocols (Figure 21) to communicate with the smart battery. The
ISL88731C is an SMBus slave device and does not initiate
communication on the bus. It responds to the 7-bit address
0b0001001_ (0x12).
Read address = 0b00010011 and
Write address = 0b00010010.
In addition, the ISL88731C has two identification (ID) registers: a
16-bit device ID register and a 16-bit manufacturer ID register.
A
HI BYTE
DATA
A
LO BYTE
DESCRIPTION
DATA
A
DRIVEN BY THE MASTER
DRIVEN BY ISL88731C
P
A
HI BYTE
DATA
N
February 8, 2011
POR STATE
P
0x0000
0x0000
0x0080
0x0049
0x0001
FN6978.2