MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet
MM912H634CV1AE
Specifications of MM912H634CV1AE
Related parts for MM912H634CV1AE
MM912H634CV1AE Summary of contents
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... MCU Test This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010-2011. All rights reserved. • Six high voltage / Wake-up inputs (L5…0) • Three low voltage GPIOs (PB2…0) • ...
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... MM912G634CM1AE -40°C to 125°C MM912G634CV1AE -40°C to 105°C MM912G634CV2AP -40°C to 105°C MM912H634CM1AE -40°C to 125°C MM912H634CV1AE -40°C to 105°C Note: 1. See Table 2. 2. The 48 kB Flash option (MM912G634) using the same S12I64 MCU with the tested FLASHSIZE reduced to 48 kB. This will limit the usable Flash area to the first 48 kB (0x3_4000-0x3_FFFF) ...
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... The device part number is following the standard scheme Product Memory Type Core Category MM- Qualified 9 = Flash HC08 Standard OTP SM- Custom Blank = ROM 12 = HC12 Device PM- Prototype Device Freescale Semiconductor Table 3: Table 3. Part Numbering Scheme f xxx r Memory Size Analog Revision A Core/Target 1 k (default 128 k MM912_634 Advance Information, Rev ...
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... Impact of Security on Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 4.38 S12 Clock, Reset and Power Management Unit (S12CPMU .236 4.39 Serial Peripheral Interface (S12SPIV5 .274 4.40 64 KByte Flash Module (S12FTMRC64K1V1 .294 4.41 Die-to-Die Initiator (D2DIV1 .327 Freescale Semiconductor Table of Contents MM912_634 Advance Information, Rev. 4.0 4 ...
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... Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 5.1 Package Dimensions .339 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 5 ...
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... VSSD2D VDDD2D VDD VDDX DGND VSENSE VS1 VS2 HS1 HS2 HSUP LIN Freescale Semiconductor PORTA DDRA Internal Bus Figure 2. Device Block Diagram MM912_634 Advance Information, Rev. 4.0 PA7 BKGD/MODC RESET RESET_A TCLK TEST_A Internal Bus ISENSEH ISENSEL LS2 PGND LS1 6 ...
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... VDDRX The device exposed pad (package option AE only) is recommended to be connected to GND. Not all pins are available for analog die option 2. See details. Freescale Semiconductor Figure 3. MM912_634 Pin Out NOTE Section 4.3.3, “Analog Die Options MM912_634 Advance Information, Rev. 4.0 Pin Assignment ...
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... Note optional filter capacitor CVSENSE is recommended to be placed between the board connector and DVSENSE to GND for increased ESD performance. Freescale Semiconductor Table 4. MM912_634 Pin Description General purpose port A input or output pin 6. See Module (S12IPIMV1) EXTAL is one of the optional crystal/resonator driver and external clock pins. On reset, all the device clocks are derived from the Internal Reference Clock and port PE may be used for general purpose I/O ...
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... ADC Reference Voltage 30 AGND Analog Ground Pin Freescale Semiconductor Table 4. MM912_634 Pin Description This pin is the device power supply pin 1. VS1 is primarily supplying the VDDX Voltage regulator and the Hall Sensor Supply Regulator (HSUP). VS1 can be sensed via a voltage divider through the AD converter. Reverse battery protection diode is required. See Section 4.5, “ ...
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... An optional filter capacitor CLX is recommended to be placed between the board connector and RLX to GND for increased ESD performance. Freescale Semiconductor Table 4. MM912_634 Pin Description This pins is the High Voltage Input 0 with the following shared functions: • Digital High Voltage Input 0. When used as digital input, a series resistor (RLX) must be used to protect against automotive transients. • ...
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... TEST — BKGD MODC PA7 — Freescale Semiconductor Table 4. MM912_634 Pin Description Low Side output 1 used to drive small inductive loads like relays. The output is short-circuit protected, includes active clamp circuitry and can be also controlled by the PWM module. See Section 4.13, “Low Side Drivers - LSx This pin is the device Low Side Ground connection ...
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... Function 1 Function 2 PA6 — PA5 — PA4 — PA3 SS PA2 SCK PA1 MOSI PA0 MISO PC1 D2DINT PC0 D2DCLK PD7-0 D2DDAT7-0 Freescale Semiconductor Table 5. Signal Properties Summary Internal Pull Resistor Power Supply CTRL VDDRX NA VDDRX NA VDDRX NA VDDRX NA VDDRX NA VDDRX NA VDDRX NA PUPCE/ ...
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... Input / Output Pins PTB[0:2] Voltage HS1 and HS2 Pin Voltage (DC) LS1 and LS2 Pin Voltage (DC) ISENSEH and ISENSEL Pin Voltage (DC) HSUP Pin Voltage (DC) VSENSE Pin Voltage (DC) Note: 8. See Section 3.9, “Additional Test Information ISO7637-2 Freescale Semiconductor Symbol V SUP(SS) V SUP(PK) V SUP(TR) V LxDC ...
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... MCU I/O and Supply Voltage (12) MCU Digital Logic Supply Voltage MCU Oscillator MM912x634xxxAE MM912x634xxxAP MCU Bus frequency MM912x634xxxAE MM912x634xxxAP Note: 12. During power up and power down sequence always V 13. f frequency ratings differ by device and is specified in BUSMAX Freescale Semiconductor Symbol V DDRX V DDD2D ILV V TEST Table 8 ...
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... SUP -40 °C T 125 °C (MM912x634xMxxx) • A -40 °C T 105 °C (MM912x634xVxxx) • A Typical values noted reflect the approximate parameter mean at T Freescale Semiconductor Table 9. Operating Conditions Symbol Table 10. Supply Currents Symbol 5.5 V, -40 °C I DDX RUN_A = 2 ...
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... VDDX VDDXinternal Normal Mode Output Current Limitation (I Stop Mode Output Voltage (I < 500 µA) VDDX Stop Mode Output Current Limitation (I VDDX Line Regulation Normal Mode VDDX Stop Mode 500 µA VDDX Freescale Semiconductor Symbol V POR V LVI V LVI_H V HVI V HVI_H V LBI V LBI_H ...
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... ILOAD = 30 mA; 5.5 V ≤ VSUP ≤ 150 °C, ILOAD = 30 mA; 3.7 V ≤ VSUP < 5 Output Voltage: (18 V V SUP Load Regulation (1.0 mA < I < 30 mA; V HSUP Hall Supply Capacitor Range External Capacitor ESR Freescale Semiconductor Symbol LD XRUN < VDDX XCRK LD XSTOP C VDDX C ...
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... Receiver Input Voltage; Receiver Dominant State Receiver Input Voltage; Receiver Recessive State Receiver Threshold Center ( TH_DOM Receiver Threshold Hysteresis (V TH_REC Voltage Drop at the serial Diode LIN Pull-up Resistor Bus Wake-up Threshold from Stop or Sleep Bus Dominant Voltage Freescale Semiconductor Symbol R DS(ON) < 9.0 V SUP - 2 SUP LIMHSX I ...
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... Internal Pull-up Resistance (V min > Input voltage > Input Capacitance Clamp Voltage when selected as analog input Analog Input impedance = 10 kOhm max, Capacitance = 12 pF Analog Input Capacitance = 12 pF Maximum current all PTB combined (VDDX capability!) Output Drive strength at 10 MHz Freescale Semiconductor Symbol V THL V THH V HYS I ...
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... RES = 2.44 mV/(GAIN*R ) SHUNT Table 24. Static Electrical Characteristics - Temperature Sensor - TSENSE Ratings (22) Internal Chip Temperature Sense Gain Internal Chip Temperature Sense Error at the end of conversion Temperature represented by a ADC Voltage of 0.150 V IN Freescale Semiconductor Symbol V ADC2p5RU N V ADC2p5ST OP LR RUNA C ADC2p5 ...
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... V IH Internal pull-down resistance (V min > input voltage > Input capacitance (24) Injection current Single pin limit Total device Limit, sum of all injected currents Note: 24. Refer to Section 3.8, “ESD Protection and Latch-up Freescale Semiconductor Symbol (22) T 1.984V Symbol = V / ADCIN) RATIO VSENSE VSENS E Er VSENSE ...
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... LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or drops of the supply voltage LVID V LVIA V LVRD V LVRA V PORD LVI POR LVR Figure 4. MC9S12I32 - Chip Power-up and Voltage Drops (not scaled) Freescale Semiconductor Table 27. IVREG Characteristics Symbol Min V 2.97 LVRXA V — LVRXD V 0.6 PORA V — PORD and V ...
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... Cyclic Sense / Forced Wake-up Timing Accuracy - trimmed Time between HSx on and Lx sense during cyclic sense HSx ON duration during Cyclic Sense HSx ON duration during Cyclic Sense - trimmed Note: 31. No trimming possible in Sleep mode. Freescale Semiconductor -40 °C T SUP °C under nominal conditions, unless otherwise noted. A Symbol ...
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... LIN signal threshold defined at each parameter. See Duty Cycle 0.778 x V REC(MAX) SUP TH = 0.616 x V DOM(MAX) SUP 7.0 V V µs SUP BIT /( BUS_REC(MIN) BIT Freescale Semiconductor Symbol t IWDTO ACT Symbol f 500 HS Symbol f LS Symbol t PROPWL BR FAST ...
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... LIN Transmitter Timing, (V from 7 See SUP Transmitter Symmetry ttran_sym < MAX(ttran_sym60%, ttran_sym40%) tran_sym60% = ttran_pdf60% - ttran_pdr60% tran_sym40% = ttran_pdf40% - ttran_pdr40% Figure 6. LIN Timing Measurements for Normal Baud Rate Freescale Semiconductor Symbol D4 Figure 9 ttran_sym Figure 5. Test Circuit for Timing Measurements MM912_634 Advance Information, Rev. 4.0 Electrical Characteristics ...
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... Figure 7. LIN Timing Measurements for Slow Baud Rate TX BUS ttran_pdf60% ttran_pdf40% Freescale Semiconductor Figure 8. LIN Receiver Timing Figure 9. LIN Transmitter Timing MM912_634 Advance Information, Rev. 4.0 Electrical Characteristics 60% 40% ttran_pdr40% ttran_pdr60% 26 ...
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... It takes one bus cycle per phrase to verify plus a setup of the command. Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by: 1 = 17200 ------------------- - t pcheck f NVMBUS Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by: Freescale Semiconductor Symbol f PTB t PDR t RISE t PDF t FALL ...
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... NVMOP 3.6.2.1.1.8 Erase P-Flash Block (FCMD=0x09) The time required to erase the P-Flash block is given by: 1 100100 + 35000 ---------------- - t pmass f NVMOP Freescale Semiconductor . NVMOP 1 ------------------- - f NVMBUS 1 ------------------- - f NVMBUS 1 ------------------- - f NVMBUS 1 ------------------- - f NVMBUS MM912_634 Advance Information, Rev. 4.0 Electrical Characteristics ...
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... The typical D-Flash programming time is given by the following equation, where N row boundary is crossed and BC row boundary is crossed: dpgm W Freescale Semiconductor 1 ------------------- - f NVMBUS 1 ------------------- - f NVMBUS 1 ------------------- - f NVMBUS ...
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... The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors, and burn-in to screen early life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. All values shown in Freescale Semiconductor 1 ...
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... MIN1 t NOM t MAX1 The relative deviation its maximum for one clock period, and decreases towards zero for larger number of clock NOM periods (N). Jitter is defined as: Freescale Semiconductor Table 40. NVM Reliability Characteristics Program Flash Arrays = 85 C (42) after up to JAVG Data Flash Array = 85 C ...
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... MHz MHz equivalent f REF BUS 3.6.2.3 Electrical Characteristics for the IRC1M Rating Internal Reference Frequency, Factory Trimmed -40 °C T 150 °C J Freescale Semiconductor j 1 = ------- - NOTE (45) Table 41. PLL Characteristics Symbol Min f 8 ...
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... Thresholds for delay measurement points Note: 50. Timing specified for equal load on all SPI output pins. Avoid asymmetric load. 3.6.2.6.1 Master Mode In Figure 12 the timing diagram for master mode with transmission format CPHA = 0 is depicted. Freescale Semiconductor Table 43. OSCLCP Characteristics Symbol f OSC i OSC t UPOSC ...
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... MSB IN2 (Input) 9 MOSI Port Data Master MSB OUT2 (Output) 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. In Table 46 the timing characteristics for master mode are listed. Freescale Semiconductor Bit MSB-1… Bit MSB-1 1 … Figure 12. SPI Master Timing (CPHA = 0) ...
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... MISO See Slave MSB (Output) Note 5 MOSI MSB IN (Input) NOTE: Not defined In Figure 15 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. Freescale Semiconductor Symbol Min f 1/2048 SCK t 2.0 SCK t — LEAD t — LAG t — ...
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... Rise and Fall Time Outputs Note: 51. 0.5 t added due to internal synchronization delay BUS 3.7 Thermal Protection Characteristics Characteristics noted under conditions 5.5 V V reflect the approximate parameter mean at T Freescale Semiconductor Bit MSB-1... 1 MSB OUT 6 Bit MSB-1… 1 Figure 15. SPI Slave Timing (CPHA = 1) Table 47 ...
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... ZAP = 125 C (53) Latch-up current ESD GUN - LIN Conformance Test Specification = 330 . discharge 150 pF, R ZAP ZAP - LIN (with or without bus filter C =220 pF) BUS - VS1, VS2 with with serial R LX Freescale Semiconductor Symbol T HTI T HTI_H SD_H T HSUPSD T HSUPSD_HYS T HSSD T HSSD_HYS ...
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... Note: 53. Input Voltage Limit = -2.5 to 7.5 V. 54. With C (10…100 nF) as part of the battery path. VBAT 55. Certification available on request 56. Tested internally only; certification pending Freescale Semiconductor Symbol (56) , unpowered, (56) , unpowered, contact (56) , powered, contact MM912_634 Advance Information, Rev. 4.0 Electrical Characteristics Value Unit ± ...
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... Additional Test Information ISO7637-2 Immunity against transients for the LIN, Lx, and VBAT, is specified according to the LIN Conformance Test Specification - Section LIN EMC Test Specification refer to the LIN Conformance Test Certification Report - available as separate document. Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 Electrical Characteristics ...
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... Freescale Semiconductor Functional Description and Application Information Section 4.39, “Serial Peripheral Interface Table 50. Device Register Memory Map Overview Module PIM (port integration module) MMC (memory map control) PIM (port integration module) ...
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... Bit 7 0x000E Reserved 0x000F W Table 55. 0x0010–0x001B Memory Map Control (MMC) Map Address Name Bit 0x0010 Reserved W Freescale Semiconductor Functional Description and Application Information NOTE Table 50 is not allocated to any module. This register Bit 6 Bit 5 Bit 4 PA6 PA5 PA4 DDRA6 DDRA5 ...
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... W Address Name Bit 7 R 0x001F IVBR W Address Name Bit 7 R 0x0020 DBGC1 ARM W R TBF 0x0021 DBGSR 0x0022 DBGTCR W Freescale Semiconductor Functional Description and Application Information Bit 6 Bit 5 Bit 4 DP14 DP13 DP12 Table 56. 0x0016–0x0019 Reserved Bit 6 Bit 5 Bit Bit 6 ...
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... Reserved 0x0033 W Table 62. 0x0034–0x003F Clock and Power Management (CPMU) Map Address Name Bit 7 R CPMU 0x0034 VCOFRQ[1:0] SYNR W Freescale Semiconductor Functional Description and Application Information Table 60. 0x0020–0x002F Debug Module (DBG) Bit 6 Bit 5 Bit Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 ...
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... W R 0x00D9 D2DCTL1 D2DIE W R 0x00DA D2DSTAT0 ERRIF W R 0x00DB D2DSTAT1 D2DIF W R RWB 0x00DC D2DADRHI W R 0x00DD D2DADRLO W Freescale Semiconductor Functional Description and Application Information Bit 6 Bit 5 Bit PORF LVRF LOCKIF 0 0 LOCKIE 0 0 PSTP 0 FM1 FM0 RTR6 RTR5 RTR4 0 ...
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... R7 0x00ED SPIDRL 0x00EE Reserved 0x00EF Reserved W Address Name Bit 0x00E0- Reserved 0x00FF W Freescale Semiconductor Functional Description and Application Information DATA[15:8] DATA[7:0] Table 65. 0x00E0–0x0E7 Reserved Bit 6 Bit 5 Bit Bit 6 Bit 5 Bit 4 SPE SPTIE MSTR CPOL 0 XFRW MODFEN BIDIROE SPPR2 SPPR1 SPPR0 ...
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... R 0 0x010E Reserved 0x010F Reserved W R NV7 0x0110 FOPT 0x0111 Reserved 0x0112 Reserved 0x0113 Reserved W Freescale Semiconductor Functional Description and Application Information Table 68. 0x0100–0x011F Flash Module (FTMRC) Bit 6 Bit 5 Bit 4 FDIVLCK FDIV5 FDIV4 KEYEN0 RNV5 RNV4 IGNSF ACCERR FPVIOL RNV6 ...
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... Reserved W Address Name Bit 0x01FD- Reserved 0x01FF W Table 73. 0x0200–0x03FF Die-To-Die Initiator Blocking and Non-Blocking Access Window Address Name Bit 7 Freescale Semiconductor Functional Description and Application Information Bit 6 Bit 5 Bit 4 PTIA6 PTIA5 PTIA4 Table 70. 0x0180–0x1EF Reserved Bit 6 Bit 5 Bit 4 ...
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... Wake Up Source Register RSR 0x15 Reset Status Register MCR 0x16 Mode Control Register LINR 0x18 LIN Register PTBC1 0x20 Port B Configuration Register 1 PTBC2 0x21 Port B Config Register 2 Freescale Semiconductor Functional Description and Application Information (57) - 0x0200–0x02FF D2D Blocking Access (D2DI HOT ERR TOV ...
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... SCI Data Register PWMCTL 0x60 PWM Control Register PWMPRCLK 0x61 PWM Presc. Clk Select Reg PWMSCLA 0x62 PWM Scale A Register PWMSCLB 0x63 PWM Scale B Register Freescale Semiconductor Functional Description and Application Information (57) - 0x0200–0x02FF D2D Blocking Access (D2DI HSHVSD HSOTIE ...
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... ADC Data Result Register 2 ADR2 (lo) 0x8B ADC Data Result Register 2 ADR3 (hi) 0x8C ADC Data Result Register 3 ADR3 (lo) 0x8D ADC Data Result Register 3 ADR4 (hi) 0x8E ADC Data Result Register 4 Freescale Semiconductor Functional Description and Application Information (57) - 0x0200–0x02FF D2D Blocking Access (D2DI Bit ...
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... ADC Data Result Reg 12 ADR14 (hi) 0xA2 ADC Data Result Reg 14 ADR14 (lo) 0xA3 ADC Data Result Reg 14 ADR15 (hi) 0xA4 ADC Data Result Reg 15 ADR15 (lo) 0xA5 ADC Data Result Reg 15 Freescale Semiconductor Functional Description and Application Information (57) - 0x0200–0x02FF D2D Blocking Access (D2DI adr4 1 adr4 ...
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... TIM InCap/OutComp Reg 0 TC1 (hi) 0xD0 TIM InCap/OutComp Reg 1 TC1 (lo) 0xD1 TIM InCap/OutComp Reg 1 TC2 (hi) 0xD2 TIM InCap/OutComp Reg 2 TC2 (lo) 0xD3 TIM InCap/OutComp Reg 2 TC3 (hi) 0xD4 TIM InCap/OutComp Reg 3 Freescale Semiconductor Functional Description and Application Information (57) - 0x0200–0x02FF D2D Blocking Access (D2DI ...
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... Trimming Reg 1 CTR2 0xF2 Trimming Reg 2 CTR3 0xF3 Trimming Reg 3 SRR 0xF4 Silicon Revision Register Note: 57. Registers not shown are reserved and must not be accessed. Freescale Semiconductor Functional Description and Application Information (57) - 0x0200–0x02FF D2D Blocking Access (D2DI tc3 7 tc3 6 tc3 ...
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... Beyond this chapter, there will be no additional note or differentiation between the different implementations. 4.3.3.1 Current Sense Module For device options with the current sense module not available, the following considerations are to be made. Freescale Semiconductor Table 75. Silicon Revision Register (SRR ...
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... New PIN PIN Option 1 name 31… 4.3.3.2.2 Register Considerations The Lx - Bit for the not available Lx input in the Lx Status Register must be ignored. Freescale Semiconductor Table 78. ISENSE - Pin Considerations New PIN name NC ISENSE feature not bonded and/or not tested. Connect PINs 40 and 41 (NC) to GND ...
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... ADC Data Result Register x 0x8C-0 x97 ADRx (lo) ADC Data Result Register x 4.3.3.2.3 Functional Considerations For the not available Lx inputs, the following functions are limited: • No Wake-up feature / Cyclic Sense • No Digital Input • No Analog Input and conversion via ADC Freescale Semiconductor L5DS W ...
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... With a high detected on the RESET_A pin, VDD>VLVR and VDDX>VLVRX the MM912_634 analog die enters in Normal mode. To avoid short-circuit conditions being present for a long time, a tVTO timeout is implemented. Once VDD < VLVR or VDDX < VLVRX with VS1 > (VLVI + VLVI_H) for more than tVTO, the MM912_634 analog die will transit directly to Sleep mode. Freescale Semiconductor = V). DD ...
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... Forced Wake-up (configurable timeout) • LIN Wake-up After Wake-up from the sources listed above or a reset condition, the device will transit to Reset mode. See Section 4.9, “Wake-up / Cyclic Sense Freescale Semiconductor NOTE for details. for details. MM912_634 Advance Information, Rev. 4.0 Modes of Operation Section 4 ...
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... Note: 62. The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode command. Two base clock cycles (fBASE) delay are required between WSR read and MCR write. Freescale Semiconductor Table 80. Operation Mode Overview Normal full full ...
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... Over-temperature Shutdown measured between the VDD and VDDX regulators HS1 HS2 HSUP C HSUP ADC2p5 C ADC Freescale Semiconductor HSUP. VSENSE. In addition, the VS1 supply can be routed to the Section 4.24, “Internal Supply Voltage Sense - BANDGAP. ADC. HVI HS1 & HS2 LVI ADC ...
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... The behavior explained previously is essential for the MC9S12I64 MCU die used, as this MCU does have an internal regulator stage, but the LVR function only active in normal modeMC9S12I64. The shutdown behavior should be considered when sizing the external capacitors C C for extended low voltage operation. VDDX Freescale Semiconductor VSUP VDDX Figure 18. Power Up / Down Sequence threshold (1) ...
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... Reset 0 0 Note: 64. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 83. Voltage Control Register (VCR VROVIE HTIE Table 84. VCR - Register Field Descriptions Description Table 85. Voltage Status Register (VSR) ...
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... Low Battery Condition - This status bit indicates a low voltage warning for VSENSE is present. Reading the register will clear the LBI flag if present. See Low Battery Condition present. LBC 1 - Low Battery Condition present. Freescale Semiconductor Table 86. VSR - Register Field Descriptions Description Section 4.26.1.2.3, “Trimming Register 2 (CTR2) Section 4.7, “Interrupts for details. ...
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... D2DINT acts as output only. The maximum allowed clock speed of the interface is limited to f 4.6.2.2 Sleep Mode While in Sleep mode, all Interface data pins are pulled down to DGND to reduce power consumption. Freescale Semiconductor Operation. NOTE MM912_634 Advance Information, Rev. 4.0 Die to Die Interface - Target MCU ...
Page 65
... RX - SCI Receive Interrupt 9 - SCI SCI - ADC Sequence Complete Interrupt 10 - LINOT LINOT - LIN Driver Over-temperature Interrupt 11 - HSOT HSOT - High Side Over-temperature Interrupt 12 - LSOT LSOT - Low Side Over-temperature Interrupt 13 - HOT HOT - HSUP Over-temperature Interrupt Freescale Semiconductor NOTE Table 87. Interrupt Source Register (ISR SCI RX TX ERR Table 88 ...
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... Voltage Status Interrupt (VSI) The Voltage Status Interrupt - VSI combines the five interrupt sources of the Voltage Status Register only available in the Interrupt Source Register (ISR). Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new Freescale Semiconductor Table 89. Interrupt Vector Register (IVR) 5 ...
Page 67
... Acknowledge the interrupt by reading the High Side Status Register - HSSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.12, “High Side Drivers - HS information. Freescale Semiconductor Section 4.5, “Power Supply for details on the Voltage Status Register including masking information. for details on the Voltage Status Register including masking information. ...
Page 68
... Acknowledge the interrupt by reading the Voltage Status Register - VSR. To issue a new interrupt, the condition has to vanish and occur again. See Section 4.5, “Power Supply Freescale Semiconductor for details on the Low Side Status Register including masking for details on the Hall Supply Register including masking for details on the Voltage Status Register including masking information ...
Page 69
... Offset 0x15 Note: 67. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Supply. Section 4.9, “Wake-up / Cyclic Sense. Table 92. Reset Status Register (RSR WDR EXR WUR MM912_634 Advance Information, Rev. 4.0 ...
Page 70
... As the VDD Regulator is shutdown once a LVRX condition is detected, The actual cause could be also a low voltage condition at the VDDX regulator. Reading the Reset Status register will clear the information inside. Writing has no effect. LVR and LVRX are masked when POR or WUR are set. Freescale Semiconductor Table 93. RSR - Register Field Descriptions Description . ...
Page 71
... The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active during STOP mode. There is no trimmed clock available during SLEEP mode. Freescale Semiconductor ) delay are required between the WSR read and MCR write. Wake Up ...
Page 72
... Cyclic Sense with periodic HS2 Cyclic Sense with periodic HS1 and HS2 on. Wake-up Input 5 Enabled - L5 Wake-up Select Bit L5WE Wake-up Disabled Wake-up Enabled Wake-up Input 4 Enabled - L4 Wake-up Select Bit L4WE Wake-up Disabled Wake-up Enabled Freescale Semiconductor Table 94. Wake-up Control Register (WCR L5WE L4WE L3WE Table 95 ...
Page 73
... R FWM W Reset 0 0 Note: 70. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 95. WCR - Register Field Descriptions Description Table 96. Timing Control Register (TCR MM912_634 Advance Information, Rev. 4.0 Wake-up / Cyclic Sense ...
Page 74
... LIN Wake-up - Wake-up caused by a LIN wake- L5WU L5 Wake-up - Wake-up caused by a state change of the L6 Input 4 - L4WU L4 Wake-up - Wake-up caused by a state change of the L5 Input 3 - L3WU L3 Wake-up - Wake-up caused by a state change of the L4 Input Freescale Semiconductor Table 97. TCR - Register Field Descriptions Description Table 98. Wake-up Source Register (WSR ...
Page 75
... Reading the WSR will clear the wake-up status bit(s). Writing will have no effect. The Wake-up Source Register (WSR) has to be read after a wake-up condition, in order to execute a new STOP mode command. Two base clock cycles (fBASE) delays are required between the WSR read and the MCR write. Freescale Semiconductor Table 99. WSR - Register Field Descriptions Description MM912_634 Advance Information, Rev ...
Page 76
... Reset 0 0 Note: 73. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor ) operating independent from the MCU based BASE ) can be configured between 10 ms and 1280 ms (typ.) using the WDTO Window WD timing (t ...
Page 77
... Watchdog Service Register - Writing this register with the correct value (0xAA alternating 0x55) while the window is open will reset the watchdog counter. Writing the register while the watchdog is disabled will have no effect. WDSR Freescale Semiconductor Table 101. WDR - Register Field Descriptions Description Table 102 ...
Page 78
... Hall Supply Over-temperature Condition present. During the event, the Hall Supply is shut down. Reading the register will 6 - HOTC clear the HOT flag if present. See Hall Supply On HSUPON 0 - Hall Supply Regulator disabled 1 - Hall Supply Regulator enabled Freescale Semiconductor Table 104. Hall Supply Register (HSR ...
Page 79
... R HSOTIE HSHVSDE W Reset 0 0 Note: 76. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 106. High Side Control Register (HSCR PWMCS2 PWMCS1 PWMHS2 MM912_634 Advance Information, Rev. 4.0 High Side Drivers - HS ...
Page 80
... HS2CL High Side 2 Current Limitation 2 - HS1CL High Side 1 Current Limitation 1 - HS2OL High Side 2 Open Load 1 - HS1OL High Side 1Open Load Freescale Semiconductor Table 107. HSCR - Register Field Descriptions Description for the Voltage Status Register. Table 108. High Side Status Register (HSSR ...
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... Low Side module. Pin Function Pin Name I/O & Priority LS1 High Voltage Output LS2 Freescale Semiconductor PWMCSx PWMLSx Low Side - Driver (active clamp) on/off open load detection current limitation ...
Page 82
... PWM enabled on LS1 (Channel as selected with PWMCS1 LS2 LS2 Enable; LSEN has to be written once to control the LS2 Driver 0 - LS1 LS1 Enable; LSEN has to be written once to control the LS1 Driver Freescale Semiconductor Table 111. Low Side Module - Memory Map 5 4 PWMCS2 ...
Page 83
... Side Drivers will automatically shut down in case of an over-voltage on one of the two regulators. The shutdown is fully handled in the analog section of the driver. This will secure the feature in case the digital logic is damaged due to the over-voltage condition. Freescale Semiconductor Table 114. Low Side Status Register (LSSR) 5 ...
Page 84
... A write to the Low Side Control Register (LSCR) will re-enable the Low Side drivers when the over-temperature condition is gone. 4.13.5 PWM Capability See Section 4.14, “PWM Control Module Freescale Semiconductor NOTE for details. The default trim is worst case (PWM8B2C). MM912_634 Advance Information, Rev. 4.0 ...
Page 85
... The PWM8B2C module does operate in Normal mode only. 4.14.1.3 Block Diagram Figure 22 shows the block diagram for the 8-bit 2-channel PWM block. PWM8B2C D2D Clock Clock Select Control Freescale Semiconductor HS, Section 4.13, “Low Side Drivers - LSx PWM Channels PWM Clock Enable Channel 1 Polarity Period and Duty ...
Page 86
... PWMDTY0 W R 0x69 Bit 7 PWMDTY1 W Note: 81. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Section 4.12, “High Side Drivers - HS, for configuration details. NOTE Table 118. PWM Register Summary CAE0 PCLK1 ...
Page 87
... PPOLx register bits can be written anytime. If the polarity changes while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition 4.14.3.1.3 PWM Clock Select (PCLKx) Each PWM channel has a choice of two clocks to use as the clock source for that channel as described by the following. Freescale Semiconductor Table 119. PWM Control Register (PWMCTL ...
Page 88
... Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channel 0. These three bits determine the rate of clock A, as shown in PCKA[2:0] PCKB2 Freescale Semiconductor NOTE and Section 4.14.4.2.6, “Center Aligned Outputs” NOTE PCKB1 PCKB0 0 0 ...
Page 89
... Clock SB = Clock PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Freescale Semiconductor Table 124. Clock A Prescaler Selects PCKA1 PCKA0 ...
Page 90
... Section 4.14.4.2.3, “PWM Period and Duty” To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: Freescale Semiconductor Table 126. PWM Scale B Register (PWMSCLB) 5 ...
Page 91
... Table 129. PWM Channel Duty Registers (PWMDTYx) (88) Offset 0x68/0x69 Bit Reset 0 0 Note: 88. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Section 4.14.4.2.7, “PWM Boundary NOTE for more information. NOTE Section 4.14.4.2.7, “PWM Boundary 5 ...
Page 92
... The scaled B clock uses clock input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 PWM Control Module (PWM8B2C) ...
Page 93
... When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. Freescale Semiconductor Clock A Clock A/2, A/4, A/6,....A/512 ...
Page 94
... The duty is controlled by a match between the duty register and the counter value, and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown in block diagram for the PWM timer. Freescale Semiconductor NOTE NOTE ...
Page 95
... Dedicated period and duty registers exist for each channel and are double buffered they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) • The channel is disabled Freescale Semiconductor Reset 8-bit Compare = PWMDTYx 8-bit Compare = PWMPERx T Q ...
Page 96
... PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop, as shown in duty register to the associated registers, as described in to the value in the period register – 1. Freescale Semiconductor NOTE Figure 24 and described in Outputs” ...
Page 97
... PWM counter decrements and matches the duty register again, the output flip-flop changes state, causing the PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count, and a load from the double buffer period and duty registers to the associated registers is performed, as described Freescale Semiconductor NOTE PWMDTYx Period = PWMPERx Figure 25 ...
Page 98
... PWM Boundary Cases Table 131 summarizes the boundary conditions for the PWM, regardless of the output mode (left aligned or center aligned). Freescale Semiconductor Duty”. The counter counts from the value in the period register and then back NOTE PWMPERx Period = PWMPERx*2 DUTY CYCLE = 75% PERIOD = 800 µ ...
Page 99
... All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured counter out of reset. • All the channels are disabled and all the counters do not count. 4.14.6 Interrupts The PWM module has no Interrupts. Freescale Semiconductor Table 131. PWM Boundary Cases PWMPERx PPOLx >$00 1 >$00 0 ...
Page 100
... When the under-voltage condition (LVI) is gone, the LIN will start operating when recessive state or on the next dominant to recessive transition. Freescale Semiconductor Section 4.18, “General Purpose I/O - PTB[0…2] Immunity. ...
Page 101
... LIN Module Enable 2 - LINEN 0 - LIN Module Disabled 1 - LIN Module Enabled LIN - Slew Rate Select 00 - Normal Slew Rate (20 kBit) 1-0 - LINSR 01 - Slow Slew Rate (10.4 kBit Fast Slew Rate (100 kBit Normal Slew Rate (20 kBit) Freescale Semiconductor Table 132. LIN Register (LINR LVSD Table 133 ...
Page 102
... Description,” for details concerning SCI operation in these modes: • 8 and 9-bit data modes • Loop mode • Single-wire mode 4.16.1.3 Block Diagram Figure 29 shows the transmitter portion of the SCI. Freescale Semiconductor Serial Communication Interface (S08SCIV4) MM912_634 Advance Information, Rev. 4.0 MCU ANALOG 102 ...
Page 103
... INTERNAL BUS M 1 BAUD RATE CLOCK PE PT SBK TXDIR BRK13 Figure 30 shows the receiver portion of the SCI. Freescale Semiconductor (WRITE-ONLY) SCID – Tx BUFFER 11-BIT TRANSMIT SHIFT REGISTER SHIFT DIRECTION T* PARITY GENERATION TE TRANSMIT CONTROL TDRE TIE TC TCIE Figure 29. SCI Transmitter Block Diagram MM912_634 Advance Information, Rev ...
Page 104
... INTERNAL BUS 16 BAUD RATE CLOCK FROM TRANSMITTER LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM RxD RX- DATA RECOVERY ACTIVE EDGE DETECT PE PT Freescale Semiconductor (READ-ONLY) DIVIDE SCID – Rx BUFFER BY 16 11-BIT RECEIVE SHIFT REGISTER M LBKDE WAKEUP ILT LOGIC RDRF RIE IDLE ILIE ...
Page 105
... SCI baud rate generator. When the SCI baud rate generator is disabled to reduce supply current. When SBR[7:0] to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in Freescale Semiconductor of this data sheet for the absolute address assignments for all SCI registers. Table 134. SCI Baud Rate Register (SCIBD (hi)) ...
Page 106
... Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number the data character, including the parity bit, is odd. Even parity means the total number the data character, including 0 the parity bit, is even Even parity. 1 Odd parity. Freescale Semiconductor Table 138. SCI Control Register 1 (SCIC1 RSRC M 0 ...
Page 107
... I/O pin. Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1 the RxD pin reverts to being a general-purpose I/O pin even Receiver off Receiver on. Freescale Semiconductor Table 140. SCI Control Register 2 (SCIC2 RIE ILIE TE 0 ...
Page 108
... To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID Receive data register empty. RDRF 1 Receive data register full. Freescale Semiconductor Table 141. SCIC2 Field Descriptions (continued) Description Operation” for more details. Section 4.16.3.2.1, “Send Break and Queued Table 142. SCI Status Register 1 (SCIS1) 5 ...
Page 109
... R LBKDIF RXEDGIF W Reset 0 0 Note: 96. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 143. SCIS1 Field Descriptions (continued) Description Table 144. SCI Status Register 2 (SCIS2 RXINV(97) RWUID 0 0 MM912_634 Advance Information, Rev. 4.0 ...
Page 110
... Reset 0 0 Note: 98. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 145. SCIS2 Field Descriptions Description Table 146. SCI Control Register 3 (SCIC3 TXDIR TXINV(99) ORIE MM912_634 Advance Information, Rev. 4.0 ...
Page 111
... Offset 0x47 Reset 0 0 Note: 100. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Serial Communication Interface (S08SCIV4) Table 147. SCIC3 Field Descriptions Description Table 148. SCI Data Register (SCID MM912_634 Advance Information, Rev ...
Page 112
... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ±4.0 percent for 9-bit data format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates normally possible to get within a few percent, which is acceptable for reliable communications ...
Page 113
... In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. Freescale Semiconductor Table 149. Break Character Length ...
Page 114
... IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one new character and has set RDRF. Freescale Semiconductor Serial Communication Interface (S08SCIV4) MM912_634 Advance Information, Rev. 4.0 ...
Page 115
... When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. Freescale Semiconductor Serial Communication Interface (S08SCIV4) MM912_634 Advance Information, Rev. 4.0 ...
Page 116
... Note: 102. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Field Analog Input Divider Ratio Selection - Lx 5 (typ.) L[5-0] 7.2 (typ) Freescale Semiconductor Section 4.9, “Wake-up / Cyclic Table 150. Lx Status Register (LXR Table 151 ...
Page 117
... Alternative PWM Functionality As an alternative routing for the PWM channel ( output, the PortB 2 (PTB2) can be configured to output one of the two PWM channels defined in the Section 4.14, “PWM Control Module configured in the Port B Configuration Register 2 (PTBC2). Freescale Semiconductor PTB2 PTB1 AD2 AD1 ...
Page 118
... Table 157. Port B Configuration Register 2 (PTBC2) (104) Offset 0x21 Reset 0 0 Note: 104. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor 5 4 PUEB1 PUEB0 0 0 Table 156. PTBC1 - Register Field Descriptions Description NOTE PWMCS 0 0 MM912_634 Advance Information, Rev ...
Page 119
... If the associated data direction bit of this pin is set read returns the value of the port register, otherwise the buffered PTB[2-0] and synchronized pin input state is read. Freescale Semiconductor Table 158. PTBC2 - Register Field Descriptions Description Section 4.14, “PWM Control Module Section 4.14, “PWM Control Module (PWM8B2C) ...
Page 120
... Block Diagram D2D Clock Timer overflow interrupt Timer channel 0 interrupt Timer channel 3 interrupt For more information see the respective functional descriptions see Freescale Semiconductor Prescaler Channel 0 16-bit Counter Channel 1 Channel 2 Channel 3 Registers Figure 33. Timer Block Diagram Section 4.19.4, “Functional Description MM912_634 Advance Information, Rev ...
Page 121
... Freescale Semiconductor Functionality. NOTE NOTE Section 4.19.6, “Interrupts. Table 161. Table 161. Module Memory Map Use Timer Compare Force Register (CFORC) Output Compare 3 Mask Register (OC3M) Output Compare 3 Data Register (OC3D) ...
Page 122
... Reset 0 0 Note: 111. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 161. Module Memory Map Use Main Timer Interrupt Flag 2 (TFLG2 IOS3 Table 163. TIOS - Register Field Descriptions ...
Page 123
... Reset 0 0 Note: 113. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 165. CFORC - Register Field Descriptions Description NOTE OC3M3 0 0 Table 167. OC3M - Register Field Descriptions Description ...
Page 124
... R 0 TEN W Reset 0 0 Note: 115. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 169. OC3D - Register Field Descriptions Description NOTE Table 170. Timer Count Register (TCNT tcnt13 tcnt12 ...
Page 125
... R OM3 OL3 W Reset 0 0 Note: 117. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 173. TSCR1 - Register Field Descriptions Description TOV3 0 0 Table 175. TTOV - Register Field Descriptions ...
Page 126
... EDGnB,EDGnA Input Capture Edge Control These four pairs of control bits configure the input capture edge detector circuits. EDGnB Freescale Semiconductor Table 177. TCTL1 - Register Field Descriptions Description NOTE Table 178. Compare Result Output Action OLn 0 Timer disconnected from output pin logic ...
Page 127
... If register TC3 = $FFFF and TCRE = 1, TOF will not be set when the timer counter register (TCNT) is reset from $FFFF to $0000. The newly selected prescale factor will not take effect until the next synchronized edge, where all prescale counter stages equal zero. Freescale Semiconductor Table 182. Timer Interrupt Enable Register (TIE ...
Page 128
... CnF to be cleared. 4.19.3.3.13 Main Timer Interrupt Flag 2 (TFLG2) (112) Offset 0xCD TOF W Reset 0 0 Note: 122. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 186. Timer Clock Selection PR1 PR0 ...
Page 129
... W Reset tc1_7 tc1_6 W Reset 0 0 Note: 124. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 190. TFLG2 - Register Field Descriptions Description NOTE tc0_13 tc0_12 tc0_11 tc0_5 tc0_4 tc0_3 ...
Page 130
... Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 4.19.4 Functional Description 4.19.4.1 General This section provides a complete functional description of the timer TIM16B4C block. Refer to the detailed timer block diagram in Figure 34 as necessary. Freescale Semiconductor tc2_13 tc2_12 tc2_11 ...
Page 131
... CnF flag. The CnI bit enables the CnF flag to generate interrupt requests. The output mode and level bits, OMn and OLn, select set, clear, toggle on output compare. Clearing both OMn and OLn disconnects the pin from the output logic. Freescale Semiconductor D2D Clock CxI ...
Page 132
... This active high output will be asserted by the module to request a timer overflow interrupt, following the timer counter overflow when the overflow enable bit (TOI) bit of TFLG2 register is set. This interrupt is serviced by the system controller. Freescale Semiconductor Table 196 lists the interrupts generated by the TIM16B4C to Table 196 ...
Page 133
... The Analog Digital Converter Module is active only in normal mode disabled in Sleep and Stop mode. 4.20.3 External Signal Description This section lists and describes the signals that do connect off-chip. controlled by the Analog Digital Converter Module. Freescale Semiconductor A/D Control Logic (ADC Wrapper) A DATAA2D ...
Page 134
... ADR2[1:0] 0x8B ADR2 (lo 0x8C ADR3 (hi ADR3[1:0] 0x8D ADR3 (lo 0x8E ADR4 (hi) W Freescale Semiconductor Table 197. ADC - Pin Functions and Priorities Description Analog Ground Connection Analog Digital Converter Regulator Filter Terminal. A capacitor C required for operation OCE ADCRST 0 0 CCNT3 0 CH12 CH11 CH5 ...
Page 135
... ADR10 (lo 0x9C ADR11 (hi ADR11[1:0] 0x9D ADR11 (lo 0x9E ADR12 (hi ADR12[1:0] 0x9F ADR12 (lo 0xA0 Reserved W R 0xA1 Reserved W R 0xA2 ADR14 (hi ADR14[1:0] 0xA3 ADR14 (lo) W Freescale Semiconductor ADR5[9:2] ADR6[9:2] ADR7[9:2] ADR8[9:2] ADR9[9:2] ADR10[9:2] ADR11[9:2] ADR12[9:2] ADR14[9:2] MM912_634 Advance Information, Rev. 4 Bit 0 135 ...
Page 136
... Analog Digital Converter in Reset Mode. All ADC registers will reset to initial values. The bit has to be cleared to allow ADC operation ADC Clock Prescaler Select (D2DCLK to ADCCLK divider) 000 - 10 001 - 8 010 - 6 2-0 011 - 4 PS2…0 100 - 2 101 - 1 110 - 1 111 - 1 Freescale Semiconductor 5 4 ADR15[9:2] Table 199. ADC Config Register (ACR OCE ADCRST Table 200 ...
Page 137
... Only writing the High Byte will start the conversion with Channel 15, if selected. Write to the Low Byte will not start a conversion. CHx Measure individual Channels by writing a sequence of one channel. Channel 15 needs to be selected in order to have the offset compensation functional. Freescale Semiconductor NOTE Table 201. ADC Status Register (ASR ...
Page 138
... The following analog Channels are routed to the analog multiplexer: Channel 0 AD0 - PTB0 Analog Input 1 AD1 - PTB1 Analog Input 2 AD2 - PTB2 Analog Input 3 AD3 - L0 Analog Input 4 AD4 - L1 Analog Input 5 AD5 - L2 Analog Input 6 AD6 - L3 Analog Input Freescale Semiconductor CC11 CC10 CC9 CC8 CC7 Table 206 ...
Page 139
... Conversion Timing The conversion timing is based on the ADCCLK generated by the ADC prescaler (PS) out of the D2DCLK signal. The prescaler needs to be configured to have the ADCCLK match the specified f Freescale Semiconductor Table 209. Analog Channels Description (133) Trimming. The reference is factory trimmed to 8 LSB. ...
Page 140
... Ch10 (sample) + 18c (conversion cycles from start to end of conversion. Example 2. Sequence of Channel 10 (VSENSE) + Channel 15 (Offset Compensation) 1c (count (sample Ch15) + 18c (conversion Ch15 (in between (count further to Ch10 is performed while converting ch15 (sample) + 18c (conversion cycles from start to end of both conversions. Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 140 ...
Page 141
... GAIN setting are implemented. 4.21.1 Register Definition 4.21.1.1 Current Sense Register (CSR) (134) Offset 0x3C CSE W Reset 0 0 Note: 134. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor ...
Page 142
... This feature should be used when implementing an external filter to the current sense ISENSEx inputs. In principal an internal charge compensation is activated in synch with the conversion to avoid the sample capacitors to be discharged by the external filter. Freescale Semiconductor Table 211. CSR - Register Field Descriptions Description (135) MM912_634 Advance Information, Rev ...
Page 143
... Typ. 0.5 -50°C 0°C Refer to the Section 4.20, “Analog Digital Converter - ADC Due to internal capacitor charging, temperature measurements are valid 200 ms (max) after system power up and wake-up. Freescale Semiconductor 1,984V 150°C Typ. 50°C 100°C 150°C Figure 38. TSENSE - Graph for details on the channel selection and analog measurement ...
Page 144
... ADCH14 under normal conditions. Any result outside the range would indicate faulty behavior of either the ADC chain or the 2p5sleep Bandgap circuity. Note: 136. The maximum allowed sample frequency for Channel 14 is limited to fCH14. Increasing the sample frequency above can result in unwanted turn off of the LS drivers due to a false VREG over-voltage. Freescale Semiconductor LBI Prescaler CH11 RATIO VSENSE Figure 39 ...
Page 145
... Step 1: First choose the right trim step by adjusting SLPBGTR[2:0] with SLPBGTRE=1, SLPBG_LOCK bit has to stay at 0. Step 2: Once the trim value is known, correct SLPBGTR[2:0], SLPBGTRE and SLPBG_LOCK bits have to be set at the same time to apply and lock the trim. Once the trim is locked, no other trim on the parameter is possible. Freescale Semiconductor ...
Page 146
... R BGTRE CTR1_6 W Reset 0 0 Note: 140. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 214. Trimming Register 0 (CTR0 WDCTRE CTR0_4 CTR0_3 Table 215. CTR0 - Register Field Descriptions Description Table 216 ...
Page 147
... Reset 0 0 Note: 141. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Freescale Semiconductor Table 217. CTR1 - Register Field Descriptions Description Table 218. Trimming Register 2 (CTR2 SLPBGTRE SLPBG_LOCK MM912_634 Advance Information, Rev. 4.0 ...
Page 148
... OFFCTR2…0 100: -23.95% 101: -15.97% 110: -7.98% 111 Spare Trim enable bit CTR3_E 2 Spare Trim bit 2 CTR3_2 Freescale Semiconductor Table 219. CTR2 - Register Field Descriptions Description Table 220. Trimming Register 3 (CTR3 OFFCTR1 OFFCTR0 CTR3_E Table 221. CTR3 - Register Field Descriptions Description MM912_634 Advance Information, Rev ...
Page 149
... Field 1 Spare Trim bit 1 CTR3_1 0 Spare Trim bit 0 CTR3_0 Freescale Semiconductor Table 221. CTR3 - Register Field Descriptions Description MM912_634 Advance Information, Rev. 4.0 149 ...
Page 150
... Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 MM912_634 - MCU Die Overview MCU ANALOG 150 ...
Page 151
... Configurable 8 or 16-bit data size • Full-duplex or single-wire bidirectional • Double-buffered transmit and receive • Master or slave mode • MSB-first or LSB-first shifting • Serial clock phase and polarity options Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 MM912_634 - MCU Die Overview 151 ...
Page 152
... The whole 256 k global memory space is visible through the P-Flash window located in the 64 k local memory map located at 0x8000 - 0xBFFF using the PPAGE register. Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 MM912_634 - MCU Die Overview ...
Page 153
... Local Memory Map 0x0000 Registers 0x0400 D-Flash 4K Bytes 0x1400 Unpaged P-Flash Page 0x0C 0x2800 RAM 6K Bytes 0x4000 Unpaged P-Flash Page 0x0D 0x8000 P-Flash window 0xC000 Unpaged P-Flash Page 0x0F 0xFFFF Freescale Semiconductor 0x0_0000 0x0_2800 0x0_4000 0x0_4400 0x0_5400 0x0_8000 0x2_0000 0x3_0000 PPAGE 0x3_4000 ...
Page 154
... Security The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 4.31.4.1, “Security”, and Section 4.40.5, Freescale Semiconductor Table 222 shows the assigned part ID number and Mask Set number. Table 222. Assigned Part ID Numbers (143) Mask Set Number ...
Page 155
... Vector base + $B6 to Vector base + $8C Vector base + $8A Low-voltage interrupt (LVI) Vector base + $88 to Vector base + $82 Freescale Semiconductor Table 224. Reset Sources and Vector Locations Reset Source Power-On Reset (POR) Low Voltage Reset (LVR) External pin RESET Illegal Address Reset Clock monitor reset ...
Page 156
... FOPT. See Table 226 and Table 227 global address 0x3_FF0E during the reset sequence. NV[2:0] in FOPT Register NV[3] in FOPT Register Freescale Semiconductor CCR Interrupt Source Mask Spurious interrupt — “Initialization”. for coding. The FOPT register is loaded from the Flash configuration field byte at Table 226 ...
Page 157
... Data direction registers for ports A, E when used as general-purpose I/O • Port input register on ports A and E • Reduced drive register on port C and D 4.28.2 Memory Map and Register Definition This section provides a detailed description of all Port Integration Module registers. Freescale Semiconductor SPI MISO MOSI SCK Synchronous Serial IF SS CPMU OSC ...
Page 158
... PTIB W 0x0122 0x17F W Reserved = Unimplemented or Reserved 4.28.2.2 Port A Data Register (PORTA) Address 0x0000 PA7 PA6 W SPI — — Function Reset 0 0 Note: 145. Read: Anytime. Write: Anytime. Freescale Semiconductor PA5 PA4 PA3 DDRA5 DDRA4 DDRA3 RDPD PTIA5 PTIA4 PTIA3 Figure 43 ...
Page 159
... CPMU OSC — — Function Reset 0 0 Note: 146. Read: Anytime. Write: Anytime. Freescale Semiconductor Table 228. PORTA Register Field Descriptions Description Table 229. Port E Data Register (PORTE — — — MM912_634 Advance Information, Rev. 4.0 Port Integration Module (S12IPIMV1) (146) ...
Page 160
... Port E Data Direction Register (DDRE) Address 0x0003 Reset 0 0 Note: 148. Read: Anytime. Write: Anytime. Freescale Semiconductor Table 230. PORTE Register Field Descriptions Description 5 4 DDRA5 DDRA4 DDRA3 0 0 Table 231. DDRA Register Field Descriptions Description Figure 45. Port E Data Direction Register (DDRE ...
Page 161
... If the CPMU OSC function is active the pull-down devices are disabled. In this case the register bit will not change. PDPEE 1 Pull-down devices enabled. 0 Pull-down devices disabled. Freescale Semiconductor Table 232. DDRE Register Field Descriptions Description Table 233. PIM Reserved Registers ...
Page 162
... Write: Unimplemented. Writing to this register has no effect. 153 Unaffected by reset Field 7–0 Port A input data— A read always returns the buffered input state of the associated pin.It can be used to detect overload or short circuit conditions on output pins. PTIA Freescale Semiconductor Table 236. Reduced Drive Register (RDRIV RDPD ...
Page 163
... This register defines whether the pin is used as an input or an output peripheral module controls the pin the contents of the data direction register is ignored (Figure 4.28.3.1.3 Input register (PTIx) This is a read-only register and always returns the buffered and synchronized state of the pin Freescale Semiconductor Table 240. Port E Input Register (PTIE ...
Page 164
... It is not recommended to write PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. Freescale Semiconductor PTIx synch. ...
Page 165
... Special Single Chip Mode (SS) A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals may also provide special debug features in this mode. Freescale Semiconductor Table 243. Glossary Of Terms Definition Address within the CPU12’s Local Address Map ...
Page 166
... Memory Map and Registers 4.29.3.1 Module Memory Map A summary of the registers associated with the S12PMMC block is shown in bits are given in the subsections that follow. Freescale Semiconductor Address Decoder & Priority Target Bus Controller P-Flash RAM Figure 47. S12PMMC Block Diagram The RESET pin is used the select the MCU’s operating mode. ...
Page 167
... W (157) Reset MODC 0 = Unimplemented or Reserved Note: 157. External signal (see Table 244). Read: Anytime. Write: Only if a transition is allowed (see The MODC bit of the MODE register is used to select the MCU’s operating mode. Freescale Semiconductor Table 245. MMC Register Summary DP14 ...
Page 168
... Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. These register bits form bits [15:8] of the local address (see DP[15:8] Bit15 Freescale Semiconductor Table 247. MODE Field Descriptions Description Figure 48) ...
Page 169
... Not visible in the global memory map. 1 Visible in the global memory map and accessible via PPAGE 0x01 Freescale Semiconductor ;Set DIRECT register to 0x80. Write once only. ;Global data accesses to the range 0xXX_80XX can be direct. ;Logical data accesses to the range 0x80XX are direct. ...
Page 170
... The fixed 16 kB page from 0xC000-0xFFFF is the page number 0x0F. 4.29.4 Functional Description The S12PMMC block performs several basic functions of the S12I sub-system operation: MCU operation modes, priority control, address mapping, select signal generation and access limitations for the system. Each aspect is described in the following subsections. Freescale Semiconductor ...
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... The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a firmware command which uses CPU instructions BDM hardware commands. See the BDM Block Guide for further details. (see Figure 51). Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 Section 4.29.6.1, “CALL and RTC 171 ...
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... Bit17 BDMPPR Register [3:0] Bit17 BDMPPR Register [3:0] Freescale Semiconductor BDM HARDWARE COMMAND Global Address [17:0] Bit14 Bit13 BDM Local Address [13:0] BDM FIRMWARE COMMAND Global Address [17:0] Bit14 Bit13 CPU Local Address [13:0] Figure 51. BDMPPR Address Mapping MM912_634 Advance Information, Rev. 4.0 ...
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... CPU and BDM Local Memory Map 0x0000 REGISTERS 0x0400 D-Flash 0x1400 Unpaged P-Flash RAM 0x4000 Unpaged P-Flash 0x8000 Unpaged P-Flash or P-Flash window 0xC000 Unpaged P-Flash 0xFFFF Freescale Semiconductor 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 0x0_8000 0x3_0000 PPAGE 0x3_4000 0x3_8000 0x3_C000 0x3_FFFF Figure 52. Local to Global Address Mapping MM912_634 Advance Information, Rev ...
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... BDM accesses to the unimplemented areas are allowed but the data will be undefined. No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block Guide). Freescale Semiconductor Figure 53 and Table 254 show the memory spaces occupied by the on-chip Table 254 ...
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... The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12, S12SBDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal resources are connected to specific target buses (see Freescale Semiconductor 0x0_0000 RAM_LOW ...
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... CALL instruction a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the time of assembly. Freescale Semiconductor CPU S12X0 MMC “ ...
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... In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 4.30.3.1.1, “Interrupt Vector Base Register (IVBR)” 4.30.1.4 Block Diagram Figure 55 shows a block diagram of the INT module. Freescale Semiconductor Table 255. Terminology Term Meaning CCR Condition Code Register (in the CPU) ...
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... Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”. This is done to enable handling of all non-maskable interrupts in the BDM firmware. Freescale Semiconductor Figure 55. INT Block Diagram Table 256. Interrupt Vector Base Register (IVBR) ...
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... Clock monitor reset 0xFFFA COP watchdog reset (Vector base + 0x00F8) Unimplemented opcode trap (Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request Freescale Semiconductor NOTE NOTE Table 258. Exception Vector Map and Priority MM912_634 Advance Information, Rev. 4.0 Source 179 ...
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... X interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. Freescale Semiconductor Table 258. Exception Vector Map and Priority (163) MM912_634 Advance Information, Rev ...
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... Flash other than allowing erasure. For more information please see 4.31.1.2.3 Low-power Modes The BDM can be used until stop mode is entered. The CPU cannot enter stop mode during BDM active mode. Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 Section 4.31.4.1, “Security”. ...
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... Memory Map and Register Definition 4.31.3.1 Module Memory Map Table 259 shows the BDM memory map when BDM is active. Global Address 0x3_FF00–0x3_FF0B 0x3_FF0C–0x3_FF0E 0x3_FF0F 0x3_FF10–0x3_FFFF Freescale Semiconductor Figure 56. Data 16-Bit Shift Register Control Instruction Code and Execution Standard BDM Firmware ...
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... R X 0x3_FF04 Reserved 0x3_FF05 Reserved W R 0x3_FF06 BDMCCR CCR7 0x3_FF07 Reserved W R BDMPPR 0x3_FF08 BPAE 0x3_FF09 Reserved 0x3_FF0A Reserved 0x3_FF0B Reserved W X Freescale Semiconductor Table 260. Registers are accessed by host-driven Table 260. BDM Register Summary BDMACT 0 SDV TRACE CCR6 CCR5 CCR4 ...
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... It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware 4 to control program flow execution. SDV 0 Data phase of command not complete 1 Data phase of command is complete Freescale Semiconductor Table 261. BDM Status Register (BDMSTS BDMACT 0 SDV ...
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... BDM Program Page Index Register (BDMPPR) Register Global Address 0x3_FF08 Table 264. BDM Program Page Register (BDMPPR BPAE W Reset Unimplemented, Reserved Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured Freescale Semiconductor Description CCR6 CCR5 CCR4 CCR3 ...
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... BDM is enabled and active immediately out of special single-chip reset. 167. This method is provided by the S12S_DBG module. Freescale Semiconductor Table 265. BDMPPR Field Descriptions Description Commands”. Target system memory includes all memory that is accessible by the CPU. Commands”. The CPU resources referred to are the accumulator (D), X index Section 4 ...
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... C8 16-bit data in Note: 168. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. Freescale Semiconductor NOTE Table 266. Table 266. Hardware Commands Data Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the None part enters active background mode ...
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... If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. Freescale Semiconductor Section 4.31.4.2, “Enabling and Activating Table 267. ...
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... Read Hardware Command Write 48-BC DELAY Firmware Command Read Firmware Command Write 76-BC Delay GO, Command TRACE Freescale Semiconductor NOTE for information on how serial clock rate is selected. 16 Bits 150-BC AT ~16 TC/Bit Delay Address Address Data Next Data Command 36-BC DELAY Next Data ...
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... The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. Freescale Semiconductor Figure 58 ...
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... Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modified , it is very helpful to provide a handshake protocol in which the host could determine when an issued command is Freescale Semiconductor High-Impedance R-C Rise ...
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... BKGD Pin READ_BYTE Byte Address Host Target Figure 62. Handshake Protocol at the Command Level Freescale Semiconductor 16 Cycles Speedup Pulse Minimum Delay From the BDM Command Figure 61. Target Acknowledge Pulse (ACK) NOTE ...
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... Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Freescale Semiconductor NOTE NOTE Procedure” ...
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... It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows: Freescale Semiconductor Pulse”. SYNC Response From the Target ...
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... SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued. Freescale Semiconductor Section 4.31.4.3, “BDM Hardware Commands” for more information on the BDM commands. ...
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... The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 196 ...
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... Force — This is valid on the first instruction boundary after a match occurs • Two types of breakpoints — CPU breakpoint entering BDM on breakpoint (BDM) — CPU breakpoint executing SWI on breakpoint (SWI) • Trigger mode independent of comparators — TRIG Immediate software trigger Freescale Semiconductor MM912_634 Advance Information, Rev. 4.0 197 ...
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... Block Diagram TAGHITS SECURE COMPARATOR A CPU BUS COMPARATOR B COMPARATOR C READ TRACE DATA (DBG READ DATA BUS) Freescale Semiconductor Section 4.32.4.5.2.1, “Normal Comparator Breakpoints Matches Enabled Possible Yes Yes Yes Only SWI Active BDM not possible when not enabled Yes ...
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... DBGBCTL SZE 0x0028 DBGCCTL 0x0029 DBGXAH W R 0x002A DBGXAM Bit 0x002B DBGXAL Bit 0x002C DBGADH Bit 0x002D DBGADL Bit 7 W Freescale Semiconductor Figure Table 269. Quick Reference to DBG Registers BDM TRIG TSOURCE Bit 14 Bit 13 Bit 12 Bit 6 Bit 5 Bit TAG BRK ...
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... When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. Freescale Semiconductor Table 269. Quick Reference to DBG Registers 6 ...