PIC32MX440F128L-80V/BG Microchip Technology, PIC32MX440F128L-80V/BG Datasheet
PIC32MX440F128L-80V/BG
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PIC32MX440F128L-80V/BG Summary of contents
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... Microchip Technology Inc. PIC32MX3XX/4XX Data Sheet High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers DS61143H ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... USB 2.0-compliant full-speed device and On-The-Go (OTG) controller • USB has a dedicated DMA channel • 3 MHz to 25 MHz crystal oscillator • Internal 8 MHz and 32 kHz oscillators © 2011 Microchip Technology Inc. PIC32MX3XX/4XX • Separate PLLs for CPU and USB clocks 2 • Two I C™ ...
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... Section 30.0 “Packaging Information” 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes 2/2 Yes Yes for details. © 2011 Microchip Technology Inc. ...
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... TABLE 2: PIC32MX USB – FEATURES Device PIC32MX420F032H 64 PT PIC32MX440F128H PT PIC32MX440F256H PT PIC32MX440F512H PT 100 PT PIC32MX440F128L 80 121 BG 100 PT PIC32MX460F256L 80 121 BG 100 PT PIC32MX460F512L 80 121 BG Legend TQFP MR = QFN Note 1: This device features 12 KB Boot Flash memory. 2: See Legend for an explanation of the acronyms. See © 2011 Microchip Technology Inc. ...
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... Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS61143H-page PIC32MX320F032H 7 PIC32MX320F064H 8 PIC32MX320F128H 9 PIC32MX340F128H 10 PIC32MX340F256H 11 PIC32MX340F512H Pins are tolerant 48 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 47 46 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 45 44 IC3/PMCS2/PMA15/INT3/RD10 U1CTS/IC2/INT2/RD9 43 42 RTCC/IC1/INT1/RD8 41 Vss OSC2/CLKO/RC15 40 39 OSC1/CLKI/RC12 SCL1/RG2 37 36 SDA1/RG3 35 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 34 U1TX/SDO1/RF3 33 32 © 2011 Microchip Technology Inc. ...
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... TQFP (General Purpose) PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/AN0/V +/CV +/PMA6/CN2/RB0 REF REF © 2011 Microchip Technology Inc. PIC32MX3XX/4XX = Pins are tolerant PIC32MX320F032H 6 PIC32MX320F064H 7 PIC32MX320F128H 8 PIC32MX340F128H 9 PIC32MX340F256H 10 PIC32MX340F512H SOSCO/T1CK/CN0/RC14 48 ...
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... AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/CN3/RB1 24 PGED1/AN0/CN2/RB0 25 DS61143H-page 8 = Pins are tolerant PIC32MX320F128L 64 PIC32MX340F128L 63 PIC32MX360F256L 62 PIC32MX360F512L © 2011 Microchip Technology Inc SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 RTCC/IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 ...
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... RE8 RE9 RA0 H RB5 RB4 RB3 RB2 RB7 K RB1 RB0 RA10 L RB6 RA9 AV SS Note 1: Refer to Table 3 for full pin names. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L RE0 RG0 RF1 ENVREG V SS RE1 RA7 RF0 V / RD5 CORE ...
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... G11 TDI/RA4 H1 AN5/C1IN+/CN7/RB5 H2 AN4/C1IN-/CN6/RB4 Connect (NC Connect (NC) H8 SDI1/RF7 H9 SCK1/INT0/RF6 H10 SCL1/RG2 H11 SCL2/RA2 J1 AN3/C2IN+/CN5/RB3 J2 AN2/C2IN-/SS1/CN4/RB2 J3 PGED2/AN7/RB7 AN11/PMA12/RB11 J6 TCK/RA1 J7 AN12/PMA11/RB12 J8 No Connect (NC Connect (NC) J10 SDO1/RF8 J11 SDA1/RG3 K1 PGEC1/AN1/CN3/RB1 K2 PGED1/AN0/CN2/RB0 K3 V +/CV +/PMA6/RA10 REF REF © 2011 Microchip Technology Inc. ...
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... Number K4 AN8/C1OUT/RB8 K5 No Connect (NC) K6 U2CTS/RF12 K7 AN14/PMALH/PMA1/RB14 U1RTS/CN21/RD15 K10 U1TX/RF3 K11 U1RX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/PMA7/RA9 REF REF © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pin Full Pin Name Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 U2RTS/RF13 L7 AN13/PMA10/RB13 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 L9 CN20/U1CTS/RD14 L10 U2RX/PMA9/CN17/RF4 L11 U2TX/PMA8/CN18/RF5 DS61143H-page 11 ...
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... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS61143H-page PIC32MX420F032H 8 PIC32MX440F128H 9 PIC32MX440F256H 10 PIC32MX440F512H Pins are tolerant 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 IC4/PMCS1/PMA14/INT4/RD11 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10 43 U1CTS/SDA1/IC2/INT2/RD9 42 RTCC/IC1/INT1/RD8 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 D+/RG2 D-/RG3 USB 34 V BUS USBID/RF3 33 32 © 2011 Microchip Technology Inc. ...
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... PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 AN5/C1IN+/V /CN7/RB5 BUSON AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/AN0/V +/CV +/PMA6/CN2/RB0 REF REF © 2011 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX420F032H 7 PIC32MX440F128H 8 PIC32MX440F256H 9 PIC32MX440F512H Pins are tolerant 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 ...
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... SS2/PMA2/CN11/RG9 TMS/RA0 17 INT1/RE8 18 INT2/RE9 19 AN5/C1IN+/V /CN7/RB5 20 BUSON AN4/C1IN-/CN6/RB4 21 AN3/C2IN+/CN5/RB3 22 AN2/C2IN-/CN4/RB2 23 PGEC1/AN1/CN3/RB1 24 PGED1/AN0/CN2/RB0 25 DS61143H-page 14 = Pins are tolerant PIC32MX440F128L 64 PIC32MX460F256L 63 PIC32MX460F512L SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 V ...
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... RA0 H RB5 RB4 RB3 RB2 RB7 K RB1 RB0 RA10 L RB6 RA9 AV SS Note 1: Refer to Table 4 for full pin names. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L RE0 RG0 RF1 ENVREG V SS RE1 RA7 RF0 V / RD5 CORE V CAP RG14 RA6 ...
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... PIC32MX3XX/4XX TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES Pin Full Pin Name Number A1 PMD4/RE4 A2 PMD3/RE3 A3 TRD0/RG13 A4 PMD0/RE0 A5 PMD8/RG0 A6 PMD10/RF1 A7 ENVREG IC5/PMD12/RD12 A10 OC3/RD2 A11 OC2/RD1 B1 No Connect (NC) B2 RG15 B3 PMD2/RE2 B4 PMD1/RE1 B5 TRD3/RA7 B6 PMD11/RF0 CAP CORE B8 PMRD/CN14/RD5 B9 OC4/RD3 B10 V SS B11 ...
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... TABLE 4: PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES (CONTINUED) Pin Full Pin Name Number K4 AN8/C1OUT/RB8 K5 No Connect (NC) K6 U2CTS/RF12 K7 AN14/PMALH/PMA1/RB14 K8 VDD K9 U1RTS/CN21/RD15 K10 USBID/RF3 K11 U1RX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/PMA7/RA9 REF REF © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pin Full Pin Name ...
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... Comparator .............................................................................................................................................................................. 125 24.0 Comparator Voltage Reference (CV REF 25.0 Power-Saving Features ........................................................................................................................................................... 129 26.0 Special Features ...................................................................................................................................................................... 131 27.0 Instruction Set .......................................................................................................................................................................... 141 28.0 Development Support............................................................................................................................................................... 147 29.0 Electrical Characteristics .......................................................................................................................................................... 151 30.0 Packaging Information.............................................................................................................................................................. 191 Index ................................................................................................................................................................................................. 209 DS61143H-page 18 ).................................................................................................................................. 127 © 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. PIC32MX3XX/4XX to receive the most current information on all of our products. DS61143H-page 19 ...
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... PIC32MX3XX/4XX NOTES: DS61143H-page 20 © 2011 Microchip Technology Inc. ...
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... Program Flash Memory Note 1: Some features are not available on all device variants. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX This document contains device-specific information for the PIC32MX3XX/4XX devices. Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX3XX/4XX family of devices ...
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... CLKO in RC and EC modes. I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. O — 32.768 kHz low-power oscillator crystal output. Analog = Analog input O = Output “Pin Diagrams” section for device pin availability. Description P = Power I = Input © 2011 Microchip Technology Inc. ...
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... INT2 43 19 Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pin Buffer Type Type B11 I ST Change notification inputs. ...
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... PORTB is a bidirectional I/O port I/O ST PORTC is a bidirectional I/O port I/O ST I/O ST I/O ST I/O ST Analog = Analog input O = Output “Pin Diagrams” section for device pin availability. Description P = Power I = Input © 2011 Microchip Technology Inc. ...
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... RF13 — 39 Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pin Buffer Type Type D9 I/O ST PORTD is a bidirectional I/O port. ...
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... I/O ST Synchronous serial data input/output for I2C1. I/O ST Synchronous serial clock input/output for I2C2. I/O ST Synchronous serial data input/output for I2C2. Analog = Analog input O = Output “Pin Diagrams” section for device pin availability. Description P = Power I = Input © 2011 Microchip Technology Inc. ...
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... PMCS2 44 70 D11 Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pin Buffer Type Type JTAG Test mode select pin. ...
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... Trace Data Bits 0- — — — K2 I/O ST Data I/O pin for programming/debugging communication channel Clock input pin for programming/debugging communication channel 1. Analog = Analog input O = Output “Pin Diagrams” section for device pin availability. Description . Power I = Input © 2011 Microchip Technology Inc. ...
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... REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pin Buffer Type Type J3 I/O ST Data I/O pin for programming/debugging communication channel 2 ...
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... PIC32MX3XX/4XX NOTES: DS61143H-page 30 © 2011 Microchip Technology Inc. ...
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... ADC module is implemented Note: The AV and AV pins must connected independent of ADC use and ADC voltage reference source. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. See SS Consider the following criteria when using decoupling ...
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... POR. for ) and fast signal transitions must IL Figure 2- Figure 2-2 within EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC32MX JP C and V specifications are met. IL and V specifications are met. IL © 2011 Microchip Technology Inc. ...
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... JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device ...
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... Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternately, inputs can be reserved by connecting the pin to V through 10k resistor and configuring SS the pin as an input. clear the © 2011 Microchip Technology Inc. ...
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... Section 27. “USB On-The-Go (OTG)” (DS61126) • Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) • Section 31. “Direct Memory Access (DMA) Controller” (DS61117) • Section 32. “Configuration” (DS61124) • Section 33. “Programming and Diagnostics” (DS61129) © 2011 Microchip Technology Inc. PIC32MX3XX/4XX web site )” (DS61109) ...
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... PIC32MX3XX/4XX NOTES: DS61143H-page 36 © 2011 Microchip Technology Inc. ...
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... FIGURE 3-1: MIPS M4K BLOCK DIAGRAM CPU MDU Execution Core (RF/ALU/Shift) System Coprocessor © 2011 Microchip Technology Inc. PIC32MX3XX/4XX - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers family of - Bit field manipulation instructions ® • MIPS16e Code Compression - 16-bit encoding of 32-bit instructions to ...
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... PIC32MX where data core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. ® Processor Core includes a multi- © 2011 Microchip Technology Inc. ...
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... Config Configuration register 16 Config1 Configuration register 1 16 Config2 Configuration register 2 16 Config3 Configuration register 3 © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers ...
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... EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) AdEL Load address alignment error Load reference to protected address AdES Store address alignment error Store to protected address DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare DS61143H-page 40 Table 3-3 Description © 2011 Microchip Technology Inc. ...
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... The majority of the power consumed by the PIC32MX3XX/4XX family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX 3.4 EJTAG Debug Support ® The MIPS32 ...
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... PIC32MX3XX/4XX NOTES: DS61143H-page 42 © 2011 Microchip Technology Inc. ...
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... The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX3XX/4XX to execute from data memory. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX 4.1 Key Features • 32-bit native data width • ...
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... DS61143H-page 44 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D008000 0x1D007FFF (2) 0x1D000000 0x00002000 0x00001FFF (2) 0x00000000 © 2011 Microchip Technology Inc. ...
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... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Physical Memory Map ...
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... DS61143H-page 46 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D020000 0x1D01FFFF (2) 0x1D000000 0x00004000 0x00003FFF (2) 0x00000000 © 2011 Microchip Technology Inc. ...
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... FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H AND PIC32MX440F128L DEVICES Virtual Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 0xBF800000 Reserved 0xBD020000 0xBD01FFFF Program Flash 0xBD000000 Reserved 0xA0008000 0xA0007FFF ...
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... DS61143H-page 48 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM (1) 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D040000 0x1D03FFFF (2) 0x1D000000 0x00008000 0x00007FFF (2) 0x00000000 © 2011 Microchip Technology Inc. ...
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... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Physical Memory Map ...
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TABLE 4-1: BUS MATRIX REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — — BMX 2000 (1) CON 15:0 — — — — 31:16 — — — — BMX 2010 (1) DKPBA 15:0 31:16 — — — — BMX ...
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... TABLE 4-2: INTERRUPT REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — — — MVEC 31:16 — — — — (2) 1010 INTSTAT 15:0 — — — — 31:16 ...
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TABLE 4-3: INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — — — MVEC 31:16 — — — — (2) 1010 INTSTAT 15:0 ...
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TABLE 4-4: INTERRUPT REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H AND PIC32MX320F128L (1) DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — — — MVEC 31:16 — — — — (2) 1010 INTSTAT 15:0 — ...
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TABLE 4-5: INTERRUPT REGISTERS MAP FOR PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — — — MVEC 31:16 — — — — (2) 1010 INTSTAT 15:0 — — — ...
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TABLE 4-6: INTERRUPT REGISTERS MAP FOR THE PIC32MX420F032H DEVICE ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — — — MVEC 31:16 — — — — (2) 1010 INTSTAT 15:0 — — — — 31:16 ...
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TABLE 4-7: TIMER1-5 REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — — 0600 T1CON 15:0 ON — SIDL TWDIS 31:16 — — — — 0610 TMR1 15:0 31:16 — — — — 0620 PR1 15:0 31:16 — — ...
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TABLE 4-8: INPUT CAPTURE1-5 REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) 2000 IC1CON 15:0 ON — SIDL 31:16 2010 IC1BUF 15:0 31:16 — — — (1) 2200 IC2CON 15:0 ON — SIDL 31:16 2210 IC2BUF 15:0 ...
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TABLE 4-9: OUTPUT COMPARE1-5 REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — — 3000 OC1CON 15:0 ON — SIDL — 31:16 3010 OC1R 15:0 31:16 3020 OC1RS 15:0 31:16 — — — — 3200 OC2CON 15:0 ON — ...
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TABLE 4-10: I2C1-2 REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — 5000 I2C1CON 15:0 ON — SIDL SCLREL 31:16 — — — 5010 I2C1STAT 15:0 ACKSTAT TRSTAT — — — — 31:16 5020 I2C1ADD 15:0 — — ...
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TABLE 4-11: UART1-2 REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) 6000 U1MODE 15:0 ON — SIDL IREN 31:16 — — — (1) 6010 U1STA 15:0 UTXISEL<1:0> UTXINV URXEN 31:16 — — — 6020 U1TXREG 15:0 — ...
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TABLE 4-12: SPI1-2 REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 FRMEN FRMSYNC FRMPOL 5800 SPI1CON 15:0 ON — SIDL DISSDO 31:16 — — — 5810 SPI1STAT 15:0 — — — 31:16 5820 SPI1BUF 15:0 31:16 — — — 5830 ...
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TABLE 4-13: ADC REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) 9000 AD1CON1 15:0 ON — SIDL 31:16 — — — (1) 9010 AD1CON2 15:0 VCFG2 VCFG1 VCFG0 OFFCAL 31:16 — — — (1) 9020 AD1CON3 15:0 ...
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TABLE 4-13: ADC REGISTERS MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 9110 ADC1BUFA 15:0 31:16 9120 ADC1BUFB 15:0 31:16 9130 ADC1BUFC 15:0 31:16 9140 ADC1BUFD 15:0 31:16 9150 ADC1BUFE 15:0 31:16 9160 ADC1BUFF 15:0 Legend unknown value on ...
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TABLE 4-14: DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — (1) 3000 DMACON 15:0 ON — SIDL SUSPEND 31:16 — — — 3010 DMASTAT 15:0 — — — 31:16 3020 DMAADDR 15:0 ...
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TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX (1) DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — 3060 DCH0CON 15:0 — — — 31:16 — — — 3070 DCH0ECON 15:0 31:16 — — — 3080 DCH0INT 15:0 ...
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TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX (1) DEVICES ONLY (CONTINUED) 31/15 30/14 29/13 28/12 31:16 3160 DCH1DSA 15:0 31:16 — — — 3170 DCH1SSIZ 15:0 — — — 31:16 — — — 3180 DCH1DSIZ 15:0 — — ...
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TABLE 4-16: DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX (1) DEVICES ONLY (CONTINUED) 31/15 30/14 29/13 28/12 31:16 — — — 3260 DCH2DPTR 15:0 — — — 31:16 — — — 3270 DCH2CSIZ 15:0 — — — 31:16 — — ...
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TABLE 4-17: COMPARATOR REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — A000 CM1CON 15:0 ON COE CPOL 31:16 — — — A010 CM2CON 15:0 ON COE CPOL 31:16 — — — A060 CMSTAT 15:0 — — SIDL Legend: ...
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TABLE 4-19: FLASH CONTROLLER REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) F400 NVMCON 15:0 WR WREN WRERR LVDERR 31:16 F410 NVMKEY 15:0 31:16 (1) F420 NVMADDR 15:0 31:16 F430 NVMDATA 15:0 31:16 NVMSRC F440 ADDR 15:0 ...
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... TABLE 4-21: PORTA REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 6000 TRISA 15:0 TRISA15 TRISA14 — — 31:16 — — — — 6010 PORTA 15:0 RA15 RA14 — ...
Page 71
... TABLE 4-23: PORTC REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 6080 TRISC 15:0 TRISC15 TRISC14 TRISC13 TRISC12 31:16 — — — — 6090 PORTC 15:0 RC15 ...
Page 72
... TABLE 4-25: PORTD REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 60C0 TRISD 15:0 TRISD15 TRISD14 TRISD13 TRISD12 31:16 — — — — 60D0 PORTD 15:0 RD15 ...
Page 73
... TABLE 4-27: PORTE REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 6100 TRISE 15:0 — — — — 31:16 — — — — 6110 PORTE 15:0 — ...
Page 74
... Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See information. TABLE 4-30: PORTF REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — ...
Page 75
TABLE 4-31: PORTF REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 6140 TRISF 15:0 — — — — 31:16 — — — — 6150 PORTF 15:0 — ...
Page 76
... TABLE 4-33: PORTG REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — 6180 TRISG 15:0 TRISG15 TRISG14 TRISG13 TRISG12 31:16 — — — 6190 PORTG 15:0 RG15 RG14 RG13 ...
Page 77
... TABLE 4-35: CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY 31/15 30/14 29/13 28/12 31:16 — — — — 61C0 CNCON 15:0 ON — SIDL — 31:16 — — — — 61D0 CNEN ...
Page 78
TABLE 4-37: PARALLEL MASTER PORT REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — — 7000 PMCON 15:0 ON — SIDL ADRMUX<1:0> 31:16 — — — — 7010 PMMODE 15:0 BUSY IRQM<1:0> 31:16 — — — — 7020 PMADDR ...
Page 79
TABLE 4-39: PREFETCH REGISTERS MAP 31/15 30/14 29/13 31:16 — — — (1) 4000 CHECON — — — 15:0 31:16 CHEWEN — — (1) 4010 CHEACC 15:0 — — — 31:16 LTAGBOOT — — (1) 4020 CHETAG 15:0 31:16 — ...
Page 80
TABLE 4-40: RTCC REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — 0200 RTCCON 15:0 ON — SIDL 31:16 — — — 0210 RTCALRM 15:0 ALRMEN CHIME PIV ALRMSYNC 31:16 HR10<3:0> 0220 RTCTIME 15:0 SEC10<3:0> 31:16 YEAR10<3:0> 0230 ...
Page 81
TABLE 4-42: DEVICE AND REVISION ID SUMMARY 31/15 30/14 29/13 28/12 31:16 VER<3:0> F220 DEVID 15:0 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits 27/11 26/10 25/9 24/8 ...
Page 82
TABLE 4-43: USB REGISTERS MAP 31/15 30/14 29/13 28/12 31:16 — — — — U1OTG 5040 (2) IR 15:0 — — — — 31:16 — — — — U1OTG 5050 IE 15:0 — — — — 31:16 — — ...
Page 83
TABLE 4-43: USB REGISTERS MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 — — — — (3) 5280 U1FRML 15:0 — — — — 31:16 — — — — (3) 5290 U1FRMH 15:0 — — — — 31:16 — — ...
Page 84
TABLE 4-43: USB REGISTERS MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 — — — — 5380 U1EP8 15:0 — — — — 31:16 — — — — 5390 U1EP9 15:0 — — — — 31:16 — — — — ...
Page 85
... NVMKEY = 0x556699AA; NVMCONSET = 0x8000; // Initiate operation while(NVMCONbits.WR==1); // Wait for current operation to complete © 2011 Microchip Technology Inc. PIC32MX3XX/4XX RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster pro- gramming times than RTSP ...
Page 86
... PIC32MX3XX/4XX NOTES: DS61143H-page 86 © 2011 Microchip Technology Inc. ...
Page 87
... Detect Brown-out Configuration Mismatch Reset Software Reset © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: • POR: Power-on Reset • MCLR: Master Clear Reset Pin • ...
Page 88
... PIC32MX3XX/4XX NOTES: DS61143H-page 88 © 2011 Microchip Technology Inc. ...
Page 89
... The CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX3XX/4XX devices generate interrupt requests in response to interrupt events from peripheral mod- ules ...
Page 90
... IPC4<28:26> IPC4<25:24> IPC5<4:2> IPC5<1:0> IPC5<12:10> IPC5<9:8> IPC5<20:18> IPC5<17:16> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8> IPC6<20:18> IPC6<17:16> IPC6<28:26> IPC6<25:24> IPC7<4:2> IPC7<1:0> IPC7<12:10> IPC7<9:8> IPC7<20:18> IPC7<17:16> © 2011 Microchip Technology Inc. ...
Page 91
... DMA3 – DMA Channel 3 FCE – Flash Control Event USB Note 1: Not all interrupt sources are available on all devices. See Features” and TABLE 2: “PIC32MX USB – Features” © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Vector IRQ Interrupt Bit Location Number Flag Enable ...
Page 92
... PIC32MX3XX/4XX NOTES: DS61143H-page 92 © 2011 Microchip Technology Inc. ...
Page 93
... Configuration” (DS61112) for help determining the best oscillator components. 4. PBCLK out is available on the OSC2 pin in certain clock modes. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX oscillator system has the following modules and features: • A total of four external and internal oscillator options as clock sources • ...
Page 94
... PIC32MX3XX/4XX NOTES: DS61143H-page 94 © 2011 Microchip Technology Inc. ...
Page 95
... Cache Control Prefetch Control Hit LRU Miss LRU Hit Logic Prefetch CTRL © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. 9.1 Features • ...
Page 96
... PIC32MX3XX/4XX NOTES: DS61143H-page 96 © 2011 Microchip Technology Inc. ...
Page 97
... INT Controller System IRQ Address Peripheral Bus Decoder Global Control (DMACON) © 2011 Microchip Technology Inc. PIC32MX3XX/4XX • Automatic Word-Size Detection: - Transfer Granularity, down to byte level - Bytes need not be word-aligned at source and destination • Fixed Priority Channel Arbitration • Flexible DMA Channel Operating Modes: ...
Page 98
... PIC32MX3XX/4XX NOTES: DS61143H-page 98 © 2011 Microchip Technology Inc. ...
Page 99
... The register interface allows the CPU to communicate with the module. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX USB module includes the following features: • USB Full-Speed Support for Host and Device • Low-Speed Host Support • USB OTG Support source ...
Page 100
... To Clock Generator for Core and Peripherals USB Suspend Sleep or Idle USB Module USB Voltage Comparators SIE Transceiver FRC Oscillator 8 MHz Typical (4) TUN<5:0> Div 2 (3) UFRCEN (6) UPLLEN (7) 48 MHz USB Clock Registers and Control Interface DMA System RAM © 2011 Microchip Technology Inc. ...
Page 101
... This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX General purpose I/O pins are the simplest of peripher- als ...
Page 102
... Each CNx pin also has a weak pull-up, which acts as a current source connected to the pin. The pull-ups are enabled by setting corresponding bit in CNPUE register. specification. Refer to IH for (e.g., 5V) on any desired 5V DD © 2011 Microchip Technology Inc. ...
Page 103
... SOSCEN SOSCI Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can oper- ate as a free-running interval timer for various timing applications and counting external events ...
Page 104
... PIC32MX3XX/4XX NOTES: DS61143H-page 104 © 2011 Microchip Technology Inc. ...
Page 105
... TxCK Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins not available on 64-pin devices. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: • ...
Page 106
... Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair. DS61143H-page 106 TMRx Sync LSHalfWord PRx Gate 1 0 Sync PBCLK 0 0 TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) Prescaler 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) © 2011 Microchip Technology Inc. ...
Page 107
... INPUT CAPTURE BLOCK DIAGRAM ICx Input Prescaler Edge Detect ICM<2:0> ICM<2:0> FEDGE ICxCON © 2011 Microchip Technology Inc. PIC32MX3XX/4XX 2. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler Capture Event modes ...
Page 108
... PIC32MX3XX/4XX NOTES: DS61143H-page 108 © 2011 Microchip Technology Inc. ...
Page 109
... The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The Output Compare module (OCMP) is used to gen- erate a single pulse or a train of pulses in response to selected time base events ...
Page 110
... PIC32MX3XX/4XX NOTES: DS61143H-page 110 © 2011 Microchip Technology Inc. ...
Page 111
... Frame Sync Control SSx/F SYNC SCKx Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The SPI module is a synchronous serial interface use- ful for communicating with external peripherals and other microcontroller devices may be Serial EEPROMs, shift registers, dis- play drivers, Analog-to-Digital Converters, etc ...
Page 112
... PIC32MX3XX/4XX NOTES: DS61143H-page 112 © 2011 Microchip Technology Inc. ...
Page 113
... C module provides complete hardware support for both Slave and Multi-Master modes of the I communication standard. Figure 18-1 illustrates the I module block diagram. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX3XX/4XX devices have up to two I interface modules, denoted as I2C1 and I2C2. Each module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data ...
Page 114
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control PBCLK Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...
Page 115
... Baud Rate Generator IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The primary features of the UART module are: • Full-duplex, 8-bit or 9-bit data transmission • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 116
... Character 1 to Transmit Shift Register TRMT bit DS61143H-page 116 bit 0 bit 1 bit 7/8 Character 1 UxTXIF Cleared by User bit 0 bit 1 bit 7/8 Character 1 Stop bit Start bit bit 0 Stop bit Character 2 Character 2 to Transmit Shift Register © 2011 Microchip Technology Inc. ...
Page 117
... RIDLE bit Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Start bit 7 Stop ...
Page 118
... PIC32MX3XX/4XX NOTES: DS61143H-page 118 © 2011 Microchip Technology Inc. ...
Page 119
... PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES PIC32MX3XX/4XX Parallel Master Port Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Key features of the PMP module include: • 8-bit,16-bit interface • programmable address lines • ...
Page 120
... PIC32MX3XX/4XX NOTES: DS61143H-page 120 © 2011 Microchip Technology Inc. ...
Page 121
... RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The following are some of the key features of this module: • Time: Hours, Minutes and Seconds • 24-Hour Format (Military Time) • Visibility of One-Half-Second Period • ...
Page 122
... PIC32MX3XX/4XX NOTES: DS61143H-page 122 © 2011 Microchip Technology Inc. ...
Page 123
... inputs can be multiplexed with other analog inputs. REF REF © 2011 Microchip Technology Inc. PIC32MX3XX/4XX • Automatic Channel Scan mode • Selectable conversion trigger source • 16-word conversion result buffer • Selectable Buffer Fill modes • Eight conversion result format options • ...
Page 124
... PIC32MX3XX/4XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (1) RC Clock T PB Note 1: See the ADC electrical characteristics for the exact RC clock value. DS61143H-page 124 ADCS<7:0> 8 ADC Conversion Clock Multiplier 2,4,..., 512 © 2011 Microchip Technology Inc. ADRC ...
Page 125
... On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. 2: Internally connected. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The PIC32MX3XX/4XX Analog Comparator module contains one or more comparator(s) that can be configured in a variety of ways. ...
Page 126
... PIC32MX3XX/4XX NOTES: DS61143H-page 126 © 2011 Microchip Technology Inc. ...
Page 127
... Steps CVRR CVRSS = REF AV SS CVRSS = 0 © 2011 Microchip Technology Inc. PIC32MX3XX/4XX The 16-tap, resistor ladder network that pro- REF vides a selectable reference voltage. Although its pri- ) mary purpose is to provide a reference for the analog comparators, it also may be used independently of them. ...
Page 128
... PIC32MX3XX/4XX NOTES: DS61143H-page 128 © 2011 Microchip Technology Inc. ...
Page 129
... Idle Mode: the system clock is derived from OSC the S . Peripherals continue to operate, but OSC can optionally be individually disabled. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX • LPRC Idle Mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can option- ally be individually disabled. This is the lowest power mode for the device with a clock running. • ...
Page 130
... For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. to OSC , the OSC oscillator Section 26.2 (WDT)”. © 2011 Microchip Technology Inc. ...
Page 131
... Prevents boot Flash memory from being modified during code execution Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write ‘1’ © 2011 Microchip Technology Inc. PIC32MX3XX/4XX PIC32MX3XX/4XX devices include several features intended to maximize application flexibility and reliabil- ity and minimize cost through elimination of external components. These are: • ...
Page 132
... PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘1’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled Debugger disabled 10 = Debugger enabled 01 = Reserved (same as ‘11’ setting Reserved (same as ‘11’ setting) DS61143H-page 132 © 2011 Microchip Technology Inc. ...
Page 133
... Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Note 1: Do not disable P (POSCMOD = 00) when using this oscillator source. OSC © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Bit Bit Bit 29/21/13/5 28/20/12/4 ...
Page 134
... Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable P (POSCMOD = 00) when using this oscillator source. OSC DS61143H-page 134 ) OSC (1) © 2011 Microchip Technology Inc. ...
Page 135
... Reserved: Write ‘1’ bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 r-1 r-1 r-1 — ...
Page 136
... Bit Value at POR: (‘0’, ‘1’ Unknown) (1) Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 r-1 r-1 r-1 — — — r-1 r-1 r-1 — — — R/P R/P R/P R/P R/P R Reserved bit Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8 (1) DEVID<27:24> Reserved bit © 2011 Microchip Technology Inc. ...
Page 137
... FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable LPRC Oscillator WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event © 2011 Microchip Technology Inc. PIC32MX3XX/4XX 1:64 Output 1 Clock 25-bit Counter 25 WDT Counter Reset Decoder FWDTPS<4:0>(DEVCFG1<20:16>) LPRC Control ...
Page 138
... Section 29.1 “DC Characteristics” is applied PU at device start-up. See PWRT for more AND PWRT on-chip regulator is enabled, Section 29.1 must never CORE (1) 3.3V PIC32MX V DD ENVREG V /V CORE CAP V SS for the full operating ranges © 2011 Microchip Technology Inc. ...
Page 139
... BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS PGEC1 PGED1 PGEC2 PGED2 TDI TDO TCK TMS TRCLK TRD0 TRD1 TRD2 TRD3 © 2011 Microchip Technology Inc. PIC32MX3XX/4XX ICSP™ Controller ICESEL JTAG Controller JTAGEN DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> Core DS61143H-page 139 ...
Page 140
... DDPSPI1 JTAGEN P = Programmable bit Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 r-x r-x r-x — — — r-x r-x r-x — — — r-x r-x r-x — — — R/W-0 r-x r-x TROEN — — Reserved bit © 2011 Microchip Technology Inc. ...
Page 141
... BGTZ Branch on Greater Than Zero Likely BGTZL Branch on Less Than or Equal to Zero BLEZ Note 1: This instruction is deprecated and should not be used. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Table 27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family core. Note: Refer to “ ...
Page 142
... LO = (int)Rs / (int) (int)Rs % (int) (uns)Rs / (uns) (uns)Rs % (uns)Rt Stop instruction execution until execution hazards are cleared Rt = Status; Status if Status PC = ErrorEPC else PC = EPC Status Status ExtractField(Rs, pos, size InsertField(Rs, Rt, pos, size PC[31:28] || offset<<2 Function = ERL = 0 EXL = 0 ERL © 2011 Microchip Technology Inc. ...
Page 143
... NOR Logical OR OR Logical OR Immediate ORI Read Hardware Register (if enabled by HWRE RDHWR Register) Note 1: This instruction is deprecated and should not be used. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Description GPR[31 PC[31:28] || offset<< Like JALR, but also clears execution and instruction hazards Like JR, but also clears execution and ...
Page 144
... Rd = (uns)Rt >> Rs[4:0] NOP Rt = (int)Rs - (int) (uns)Rs - (uns)Rd Mem[Rs+offset Mem[Rs+offset Mem[Rs+offset Orders the cached coherent and uncached loads and stores for access to the shared memory SystemCallException TrapException (int)Immed TrapException Function , Rd] PSS || Rt sa-1..0 31.. Rs-1..0 31.. bit mem[Rs+offset> bit © 2011 Microchip Technology Inc. ...
Page 145
... Write to GPR in Previous Shadow Set WRPGPR Word Swap Bytes Within Halfwords WSBH Exclusive OR XOR Exclusive OR Immediate XORI Note 1: This instruction is deprecated and should not be used. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Description if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs >= (uns)Rt TrapException if (int)Rs < ...
Page 146
... PIC32MX3XX/4XX NOTES: DS61143H-page 146 © 2011 Microchip Technology Inc. ...
Page 147
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2011 Microchip Technology Inc. PIC32MX3XX/4XX 28.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 148
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2011 Microchip Technology Inc. ...
Page 149
... Microchip Technology Inc. PIC32MX3XX/4XX 28.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 150
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2011 Microchip Technology Inc. ...
Page 151
... Maximum allowable current is a function of device maximum power dissipation (see 3: See the “Pin Diagrams” section for the 5V tolerant pins. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX (Note 3)......................................... -0. ≥ 2.3V (Note 3)........................................ -0.3V to +5.5V ...
Page 152
... O (T – T )/θ Max. Unit Notes 40 — °C — °C — °C — °C/W 1 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +105°C for V-Temp A Units Conditions V — V — V — V/ms — © 2011 Microchip Technology Inc. ...
Page 153
... Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX -40°C ≤ T ≤ +85°C for Industrial A -40° ...
Page 154
... System clock is enabled and DLE . Conditions 2.3V — 4 MHz 3.6V 2.3V — 20 MHz (Note 3) 3.6V 2.3V — 60 MHz (Note 3) 3.6V 2.3V — 80 MHz 3.6V 2.3V LPRC (31 kHz) 3.3V (Note 3) 3.6V © 2011 Microchip Technology Inc. ...
Page 155
... Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: Data is characterized at +70°C and not tested. Parameter is for design guidance only. 6: This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX -40°C ≤ T ≤ +85°C for Industrial A -40° ...
Page 156
... PD ADC: ΔI (Notes ADC ADC: ΔI (Notes 3, 4) ADC ADC: ΔI (Notes 3, 4) ADC © 2011 Microchip Technology Inc. ...
Page 157
... Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 158
... Industrial Operating temperature A -40°C ≤ T ≤ +105°C for V-Temp A Min. Typical Max. Units 2.0 — 2.3 V Conditions 3 2 - - - - Conditions — © 2011 Microchip Technology Inc. ...
Page 159
... TABLE 29-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS DC CHARACTERISTICS Required Flash wait states 0 Wait State 1 Wait State 2 Wait States Note 1: 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX (3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min ...
Page 160
... Industrial Operating temperature A -40°C ≤ T ≤ +105°C for V-Temp A Min. Typical Max. Units 1.62 1.80 1.98 V μ — Capacitor must be low series resistance (< 1 Ohm) — 64 — ms ENVREG = 0 © 2011 Microchip Technology Inc. Comments (Note 2) Max 1)V ICM ...
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... SCLx, SDAx B Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-2: EXTERNAL CLOCK TIMING OS20 OSC1 © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Load Condition 2 – for OSC2 Pin L ...
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... MHz HS (Note 5) 25 MHz HSPLL (Notes 4, 5) 100 kHz S (Note 5) OSC — — See parameter OS10 for F OSC value — (Note 5) 0. (Note 5) OSC — T (Note 5) OSC — ms (Note 5) — +25°C A (Note 5) ). This parameter is OSC © 2011 Microchip Technology Inc. ...
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... AC CHARACTERISTICS Operating temperature Param. Characteristics No. (1) LPRC @ 31.25 kHz F21 LPRC Note 1: Change of LPRC frequency as V © 2011 Microchip Technology Inc. PIC32MX3XX/4XX = 2.3V TO 3.6V) DD Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ (1) Min ...
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... T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +105°C for V-Temp A (2) (1) Min. Typical — 5 — 5 — 5 — — 2 — Max. Units Conditions < 2. > 2. < 2. > 2.5V DD — ns — — T — SYSCLK © 2011 Microchip Technology Inc. ...
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... Note 1: The Power-up period will be extended if the power-up sequence completes before the device exits from BOR ( Includes interval voltage regulator stabilization delay. 3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX SYSDLY ...
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... CPU starts fetching code ≤ +85°C for Industrial A ≤ +105°C for V-Temp A Units Conditions μs -40°C to +85°C ms -40°C to +85°C — -40°C to +85°C μs -40°C to +85°C μs -40°C to +85°C © 2011 Microchip Technology Inc. ...
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... CKEXTMRL Clock Edge to Timer Increment Note 1: Timer1 is a Type A. 2: This parameter is characterized, but not tested in manufacturing prescale value (1, 8, 64, 256) © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T ...
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... V-Temp A (1) Min. Max. Units [(12 )/N] PB — [(12 )/N] — [(Greater — )/ [(Greater — )/ — 1 Conditions N = prescale ns Must also meet value parameter ( 16, TB15. 32, 64, 256) ns Must also meet parameter TB15 > 2. < 2.7V — — PB © 2011 Microchip Technology Inc. ...
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... CC Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX IC10 IC11 IC15 -40°C ≤ T ≤ +85°C for Industrial A -40° ...
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... Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) (2) Min Typical — — 50 — -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +105°C for V-Temp A Max Units Conditions 25 ns — — ns — © 2011 Microchip Technology Inc. ...
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... Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX SP10 SP21 SP20 SP20 SP21 ...
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... Max. Units Conditions — ns — — ns — — ns See parameter DO32 ns — See parameter DO31 ns — See parameter DO32 ns — See parameter DO31 ns V > 2. < 2. — ns — — > 2.7V DD — < 2.7V DD — > 2.7V DD — < 2.7V DD © 2011 Microchip Technology Inc. ...
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... Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX SP70 SP72 SP73 SP73 ...
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... T ≤ +105°C for V-Temp A Max. Units Conditions — ns — — ns — — ns — 10 — ns See parameter DO32 — ns See parameter DO31 > 2. < 2.7V DD — ns — — ns — — ns — — — ns — ns — 25 © 2011 Microchip Technology Inc. ...
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... FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCLx IM11 IM10 SDAx In IM40 SDAx Out Note: Refer to Figure 29-1 for load conditions. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 ...
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... After this period, the first clock pulse is μs generated. μs μs μs — μ — — ns μs The amount of time the μs bus must be free before a new μs transmission can start. pF — ns — © 2011 Microchip Technology Inc. ...
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... FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCLx IS30 IS31 SDAx In IS40 SDAx Out Note: Refer to Figure 29-1 for load conditions. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX IS33 IS11 IS10 IS26 IS25 IS40 IS34 Stop Condition IS21 IS33 IS45 ...
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... Only relevant for Repeated Start condition After this period, the first clock pulse is generated — — — ns μs The amount of time the bus μs must be free before a new transmission can start. μs pF — © 2011 Microchip Technology Inc. ...
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... These parameters are not characterized or tested in manufacturing. 2: With no missing codes. 3: These parameters are characterized, but not tested in manufacturing. 4: Characterized with 1 kHz sinewave. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40° ...
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... LSb V — — — — 55 58.5 — dB 9.0 9.5 — bits Conditions (Note 0V, INL 2.5V to 3.6V DD (Note 0V, INL 2.5V to 3.6V DD (Notes 2, 0V, INL 2.5V to 3.6V DD (Note 0V, INL 2.5V to 3.6V DD (Note 3) Guaranteed (Notes 3, 4) (Notes 3, 4) © 2011 Microchip Technology Inc. ...
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... Up to 300 ksps 200 ns 200 ns Note 1: External V - and V + pins must be used for correct operation. REF REF 2: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX (2) R Max V ADC Channels Configuration S DD 500Ω 3. 5.0 kΩ ...
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... T — — AD 0.5 T — 1.5 T — — 0.5 T — — AD μs — — 2 © 2011 Microchip Technology Inc. Conditions See Table 29-35 and Note 2 See Note 3 — 3. 2.5V to 3.6V DD must be ≥ 132 T SAMP ns. Auto-Convert Trigger (SSRC<2:0> = 111) not selected ...
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... Family Reference Manual”. 3 – Software clears ADxCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One T for end of conversion. AD © 2011 Microchip Technology Inc. PIC32MX3XX/4XX AD55 described in Section 17. “ ...
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... Convert bit 8. 5 – Convert bit 0. 6 – One T for end of conversion – Begin conversion of next channel. 8 – Sample for time specified by SAMC<4:0>. DS61143H-page 184 AD55 AD55 described in Section 17. “10-bit Analog-to-Digital Converter (ADC)” SAMP T SAMP T CONV © 2011 Microchip Technology Inc. ...
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... Tcs CS Active Time PS6 T WR Active Time WR PS7 T RD Active Time RD Note 1: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX PS6 PS4 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) Min. Typical 20 — ...
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... T ≤ +85°C for Industrial A -40°C ≤ T ≤ +105°C for V-Temp A Max. Units Conditions — — — — — — — — — — ns — — — — — ns — — ns — © 2011 Microchip Technology Inc. ...
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... Data Out Valid before PMWR or DVSU PMENB goes Inactive (data setup time) PM13 T PMWR or PMEMB Invalid to Data DVHOLD Out Invalid (data hold time) Note 1: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Address PM2 + PM3 Address<7:0> ...
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... Voltage on V must USB be in this range for proper USB operation. V — V — V The difference between D+ and D- must exceed this value while VCM is met. V — Ω — V 1.5 kΩ load connected to 3.6V. V 1.5 kΩ load connected to ground. © 2011 Microchip Technology Inc. ...
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... TDO 3-State Delay Time from TDOZSTATE Falling TCK EJ8 T TRST Low Time TRSTLOW EJ9 T TAP Signals Rise/Fall Time, All RF Input and Output Note 1: These parameters are characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX T TCKeye T T TCKhigh TCKlow T Tsetup Thold ...
Page 190
... PIC32MX3XX/4XX NOTES: DS61143H-page 190 © 2011 Microchip Technology Inc. ...
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... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. PIC32MX3XX/4XX Example PIC32MX360F 512H-80I/PT ...
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... PIC32MX3XX/4XX 30.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [[ PP %RG\ PP >74)3@ 1RWH NOTE 1 c β 1RWHV DS61143H-page 192 E E1 NOTE 2 A φ α A2 © 2011 Microchip Technology Inc. ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. PIC32MX3XX/4XX DS61143H-page 193 ...
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... PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 194 © 2011 Microchip Technology Inc. ...
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... Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. PIC32MX3XX/4XX DS61143H-page 195 ...
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... PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 196 © 2011 Microchip Technology Inc. ...
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... PP %RG\ PP >74)3@ 1RWH NOTE 1 c β 1RWHV © 2011 Microchip Technology Inc. PIC32MX3XX/4XX E E1 NOTE 2 A φ α A2 DS61143H-page 197 ...
Page 198
... PIC32MX3XX/4XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61143H-page 198 © 2011 Microchip Technology Inc. ...
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... Note: © 2011 Microchip Technology Inc. PIC32MX3XX/4XX DS61143H-page 199 ...
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... PIC32MX3XX/4XX Note: DS61143H-page 200 © 2011 Microchip Technology Inc. ...