SM72442MT/NOPB National Semiconductor, SM72442MT/NOPB Datasheet - Page 10

• Manufacturer Part Number: SM72442MT/NOPB
• Description: PV DMPPT Controller - Solar
• Manufacturer: National Semiconductor
• Series: SolarMagic™r

Specifications of SM72442MT/NOPB

• Applications: Controller, Photovoltaic Solar Panels
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 4
• Voltage - Output: -
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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reg1 Register Description
reg3 Register Description
reg4 Register Description
reg5 Register Description
55:47
44:43
41:40
39:30
29:20
19:17
16:14
55:40
39:30
29:20
19:10
39:30
29:20
19:10
55:32
31:24
23:16
Bits
13:5
Bits
Bits
15:8
Bits
9:0
9:0
7:0
46
45
42
41
40
4
3
2
1
0
pass_through_se
overide_adcprog
pass_through_m
bb_in_ptmode_s
clk_oe_manual
power_thr_sel
Open Loop
Vout offset
vout_max
Iout offset
operation
Vin offset
iout_hi_th
iout_lo_th
iout_max
dc_open
bb_reset
Iin offset
mppt_ok
iin_hi_th
iin_lo_th
RSVD
RSVD
RSVD
RSVD
RSVD
anual
Field
Field
Field
Field
tdoff
tdon
Vout
pt_n
Iout
Vin
Iin
el
l
Reset Value
Reset Value
Reset Value
Reset Value
10'd1023
10'd1023
10'd40
10'd24
10'd40
10'd24
9'hFF
10'h0
10'h0
10'h0
10'h0
24'd0
15'd0
1'h0
1'h0
9'd0
1'b0
1'b0
2'd0
1'b0
2'd0
3'h3
3'h3
1'b0
1'b0
1'b0
1'b0
1'b0
8'h0
8'h0
8'h0
8'h0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
R
R
R
R
R
R
Register override alternative for ADC2[8:7] when reg3
Control Panel Mode when pass_through_sel bit is 1'b1
Open Loop operation (MPPT disabled, receives duty
Register override alternative when reg3[46] is set for
Register override alternative when reg3[46] is set for
Register override alternative for ADC2[9] when reg3
cycle command from reg 3b13:5); set to 1 and then
When set to 1'b1,the below overide registers used
maximum current threshold instead of ADC ch4
maximum voltage threshold instead of ADC ch0
assert & deassert bb_reset to put the device in
Enable the PLL clock to appear on pin 5
Overrides PM pin 28 and use reg3[3]
Internal mppt_start signal (test only)
over voltage protection input to IC
[46] is set ( 5%,10%,25% or 50%)
Current out high threshold for start
Current out low threshold for start
Current in high threshold for start
Open loop duty cycle (test only)
Current in low threshold for start
[46] is set ( 1/2^^5 or 1/2^^6 )
Bit Field Description
Bit Field Description
Bit Field Description
Bit Field Description
openloop (test only)
Dead time Off Time
Dead time On time
Voltage out offset
Current out offset
Voltage in offset
Current in offset
instead of ADC
Voltage out
Current out
Voltage in
Current in
Reserved
Reserved
Reserved
Soft reset
Reserved
Reserved