SM72442MT/NOPB National Semiconductor, SM72442MT/NOPB Datasheet - Page 11

• Manufacturer Part Number: SM72442MT/NOPB
• Description: PV DMPPT Controller - Solar
• Manufacturer: National Semiconductor
• Series: SolarMagic™r

Specifications of SM72442MT/NOPB

• Applications: Controller, Photovoltaic Solar Panels
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 4
• Voltage - Output: -
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Using the I2C port, the user will be able to control the duty
cycle of the PWM signal. Input and output voltage and current
offset can also be controlled using I2C on register 4. Control
registers are available for additional flexibility.
The thresholds iin_hi_th, iin_lo_th, iout_hi_th, iout_lo_th, in
reg5 are compared to the values read in by the ADC on the
AIIN and AIOUT pins. Scaling is set by the scaling of the ana-
log signal fed into AIIN and AIOUT. These 10–bit values
determine the entry and exit conditions for MPPT.
COMMUNICATING WITH THE SM72442
The SCL line is an input, the SDA line is bidirectional, and the
device address can be set by I2C0, I2C1 and I2C2 pins. Three
device address pins allow connection of up to 7 SM72444s to
the same I2C master. A pull-up resistor (10k) to a 5V supply
is used to set a bit 1 on the device address. Device addressing
for slaves are as follows:
I2C0
0
0
0
1
1
1
1
I2C1
0
1
1
0
0
1
1
I2C2
1
0
1
0
1
0
1
FIGURE 11. I2C Read Sequence
Hex
0x1
0x2
0x3
0x4
0x5
0x6
0x7
11
The data registers in the SM72442 are selected by the Com-
mand Register. The Command Register is offset from base
address 0xE0. Each data register in the SM72442 falls into
one of two types of user accessibility:
1) Read only (Reg0, Reg1)
2) Write/Read same address (Reg3, Reg4, Reg5)
There are 7 bytes in each register (56 bits), and data must be
read and written in blocks of 7 bytes.
ordering of the bytes transmitted in each frame and the bits
within each byte. In the read sequence depicted in
11
starting from the LSByte, DATA1, and ending with MSByte,
DATA7. In the write sequence depicted in
bytes are transmitted in Frames 4 through 11. Only the
100kHz data rate is supported. Please refer to “The I2C Bus
Specification” version 2.1 (Doc#: 939839340011) for more
documentation on the I2C bus.
the data bytes are transmitted in Frames 5 through 11,
FIGURE 10. Endianness Diagram
Figure 10
Figure
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12, the data
depicts the
30134316
Figure