DS26303LN-75+ Maxim Integrated Products, DS26303LN-75+ Datasheet - Page 13

• Manufacturer Part Number: DS26303LN-75+
• Description: IC LIU E1/T1/J1 3.3V 144-ELQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26303LN-75+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RLOS1/TECLK
RNEG1/CV1
RNEG2/CV2
RNEG3/CV3
RNEG4/CV4
RNEG5/CV5
RNEG6/CV6
RNEG7/CV7
RNEG8/CV8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RLOS2
RLOS3
RLOS4
RLOS5
RLOS6
RLOS7
RLOS8
NAME
MCLK
PIN
112
105
141
110
103
143
113
106
140
41
34
76
69
39
32
78
71
10
42
35
75
68
4
6
3
tri-state
tri-state
TYPE
O,
O,
O
O
I
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Receive Negative-Data Output for Channel 1 to 8/Code
Violation for Channel 1 to 8
RNEG[1:8]: In dual-rail mode, this output indicates a negative
pulse on RTIPn/RRINGn. If a given receiver is in power-down
mode, the corresponding RNEGn pin is high impedance.
CV[1:8]: In single-rail mode, bipolar violation, code violation, and
excessive zeros are reported by driving CVn high for one clock
cycle. If HDB3 or B8ZS encoding is not selected, this pin indicates
only BPVs.
Note: During an RLOS condition, the RNEGn/CVn output remains
active.
Receive Clock for Channel 1 to 8. The receive data
RPOSn/RNEGn or RDATn is clocked out on the rising edge of
RCLKn. RCLKn can be inverted. If a given receiver is in power-
down mode, RCLKn is high impedance.
Master Clock. This is an independent free-running clock that can
be a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz
±50ppm for T1 mode. The clock selection is available by
MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be
internally adapted to 1.544MHz and a multiple of 1.544MHz can
be internally adapted to 2.048MHz. In hardware mode, internal
adaptation is not available so the user must provide 2.048MHz
±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode.
Loss-of-Signal Output/T1-E1 Clock
RLOS1: This output goes high when there are no transitions on
the receiveline over a specified interval. The output goes low when
there is sufficient ones density on the receiveline. The RLOS
assertion and desertion criteria are described in the Functional
Description section. The RLOS outputs can be configured to
comply with T1.231, ITU-T G.775, or ETS 300 233. In hardware
mode, ETS 300 233 “RLOS Criteria” is not available.
TECLK: When enabled (MC.TECLKE is set), this output becomes
a T1- or E1-programmable clock output. For T1 or E1 frequency
selection, see the
hardware mode.
Loss-of-Signal Output
RLOS[2:8]: RLOS2: This output goes high when there are no
transitions on the receiveline over a specified interval. The output
goes low when there is sufficient ones density on the receiveline.
The RLOS assertion and desertion criteria are described in the
Functional Description (Section 6). The RLOS outputs can be
configured to comply with T1.231, ITU-T G.775, or ETS 300 233.
In hardware mode, ETS 300 233 “RLOS Criteria” is not available.
13 of 101
CCR
register. This option is not available in
FUNCTION
MC
bits