DS26303LN-75+ Maxim Integrated Products, DS26303LN-75+ Datasheet - Page 69

• Manufacturer Part Number: DS26303LN-75+
• Description: IC LIU E1/T1/J1 3.3V 144-ELQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26303LN-75+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP Exposed Pad, 144-eLQFP, 144-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After configuring these bits, the pattern must be loaded into the BERT. This is accomplished through a 0-to-1
transition on BCR.TNPL and BCR.RNPL
Monitoring the BERT requires reading the
when the bit-error counter is 1 or more. The OOS is 1 when the receive pattern generator is not synchronized to
the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64-bit window. The receive
BERT bit-count register (RBCR) and the receive BERT bit-error count register (RBECR) are updated upon the
reception of a performance-monitor update signal (e.g., BCR.LPMU). This signal updates the registers with the
values of the counters since the last update and resets the counters.
6.9.2 BERT Interrupt Handling
There are four BERT events that can potentially trigger an interrupt. A performance monitoring update, a bit error, a
non-zero bit error count, or an Out Of Synchronization (OOS). The interrupt functions as follows:
•
•
•
6.9.3 Receive Pattern Detection
The receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial x
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to 1 if the
next 14 bits are all 0s. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is forced to
1 if bits 1 through 31 are all 0s. Depending on the type of pattern programmed, pattern detection performs either
PRBS synchronization or repetitive pattern synchronization.
6.9.3.1
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
re-synchronization is initiated. Automatic pattern resynchronization can be disabled.
See
When a status bit (BSR:PMS, BEC, or OOS) changes on an interruptible event, the corresponding interrupt
status bit (BSRL.PMSL BEL, BECL, or OOSL) is set. The INTB pin will go low if the event is enabled through
the corresponding interrupt-enable bit (BSRIE.PMSIE BEIE, BECIE, or OOSIE).
When an interrupt occurs, the host processor must read the interrupt status register (BSRL) to determine the
source of the interrupt. If the interrupt status registers are set for clear-on-read (GISC.CWE reset), the read
also clears the Interrupt Status register which clears the output INTB pin. If the interrupt status registers are set
for (GISC.CWE set), a 1 must be written to the interrupt status bit (BSRL.PMSL BEL, BECL, or OOSL) in order
to clear it which clears the output INTB pin.
Subsequently, the host processor can read the status register (BSR) to check the real-time status of the event.
Figure 6-12
Receive PRBS Synchronization
n
+ x
for the PRBS synchronization diagram.
y
+ 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
BSR
register that contains the BEC bit and the OOS bit. The BEC bit is 1
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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