DS26324GNA3+ Maxim Integrated Products, DS26324GNA3+ Datasheet
DS26324GNA3+
Specifications of DS26324GNA3+
Related parts for DS26324GNA3+
DS26324GNA3+ Summary of contents
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Rev 3/11 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit GENERAL DESCRIPTION The DS26324 is a 16-channel short-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of applications are supported impedance matching. ...
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STANDARDS COMPLIANCE ........................................................................................................ 6 1 ELECOM PECIFICATIONS COMPLIANCE 2 DETAILED DESCRIPTION ............................................................................................................ 7 3 BLOCK DIAGRAMS ...................................................................................................................... 8 4 PIN DESCRIPTION ...................................................................................................................... 10 5 FUNCTIONAL DESCRIPTION ..................................................................................................... 17 5 ...................................................................................................................... 17 ORT PERATION 5.1.1 Serial ...
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Select-DR-Scan ............................................................................................................................. 92 7.1.4 Capture-DR ................................................................................................................................... 92 7.1.5 Shift-DR ......................................................................................................................................... 92 7.1.6 Exit1-DR ........................................................................................................................................ 92 7.1.7 Pause-DR ...................................................................................................................................... 92 7.1.8 Exit2-DR ........................................................................................................................................ 92 7.1.9 Update-DR..................................................................................................................................... 92 7.1.10 Select-IR-Scan............................................................................................................................... 93 7.1.11 Capture-IR ..................................................................................................................................... 93 7.1.12 Shift-IR .......................................................................................................................................... 93 7.1.13 Exit1-IR.......................................................................................................................................... ...
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Figure 3-1. Block Diagram ..................................................................................................................................... 8 Figure 3-2. Receive Logic Detail ............................................................................................................................ 9 Figure 3-3. Transmit Logic Detail ........................................................................................................................... 9 Figure 5-1. Serial Port Operation for Write Access ............................................................................................... 17 Figure 5-2. Serial Port Operation for Read Access with CLKE ...
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Table 4-1. Pin Descriptions .................................................................................................................................. 10 Table 5-1. Parallel Port Mode Selection and Pin Functions ................................................................................... 18 Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters ........................................... 21 Table 5-3. Registers Related to Control of DS26324 Transmitters ........................................................................ 21 Table 5-4. ...
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STANDARDS COMPLIANCE 1.1 Telecom Specifications compliance The DS26324 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1 and E1 Specifications and relevant sections that are applicable to the DS26324. • T1-Related Telecommunications Specifications • ANSI ...
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DETAILED DESCRIPTION The DS26324 is a single-chip, 16-channel, short-haul line interface unit for T1 (1.544Mbps) and E1 (2.048Mbps) applications. Sixteen independent receivers and transmitters are provided in a single TE-CSBGA package. The LIUs can be individually selected for T1, ...
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BLOCK DIAGRAMS Figure 3-1. Block Diagram TYPICAL OF ALL 16 CHANNELS RRING RTIP TRING TTIP OE Reset Reset DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit T1CLK E1CLK MUX VCO/PLL Unframed All Ones Insertion Control Port Interface and Interrupt ...
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Figure 3-2. Receive Logic Detail RCLK Excessive Zero Detect T1.231 POS NEG Decoder (G.703, T1.102) BPVs, Code Violatiions Figure 3-3. Transmit Logic Detail To Remote Loopback BPV Insert DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit NRZ Data B8ZS/HDB3/AMI BPV/CV/EXZ ...
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PIN DESCRIPTION Table 4-1. Pin Descriptions NAME PIN TTIP1 E1 TTIP2 F1 TTIP3 K1 TTIP4 L1 TTIP5 T5 TTIP6 T6 TTIP7 T10 TTIP8 T11 Analog TTIP9 M16 TTIP10 L16 TTIP11 G16 TTIP12 F16 TTIP13 A12 TTIP14 A11 TTIP15 A7 ...
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NAME PIN TYPE Analog RESREF R9 input RRING1 A2 RRING2 C2 RRING3 H2 RRING4 N2 RRING5 R1 RRING6 R3 RRING7 R8 RRING8 R13 Analog input RRING9 T15 RRING10 P15 RRING11 J15 RRING12 D15 RRING13 B16 RRING14 B14 RRING15 B9 RRING16 ...
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NAME PIN TYPE TCLK1 F5 TCLK2 G4 TCLK3 G9 TCLK4 H6 TCLK5 M7 TCLK6 L8 TCLK7 L10 TCLK8 P9 TCLK9 K11 TCLK10 K12 TCLK11 F14 TCLK12 E12 TCLK13 C11 TCLK14 D12 TCLK15 N7 TCLK16 D11 RPOS1/RDATA1 F4 RPOS2/RDATA2 F3 RPOS3/RDATA3 ...
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NAME PIN TYPE RCLK1 D3 RCLK2 G6 RCLK3 K3 RCLK4 K5 RCLK5 P5 RCLK6 M8 RCLK7 P10 RCLK8 P13 O, tri-state RCLK9 L13 RCLK10 K14 RCLK11 G13 RCLK12 F12 RCLK13 E8 RCLK14 E9 RCLK15 F8 RCLK16 E6 MCLK H12 I ...
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NAME PIN TYPE SCLK/ALE/ASB N14 RDB/RWB H14 SDI/WRB/DSB G14 SD0/RDYB/ACKB C13 INTB D7 open drain DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit Shift Clock. In the serial host mode, this pin is the serial clock. Data on SDI is ...
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NAME PIN TYPE D7/AD7 N3 D6/AD6 P3 D5/AD5 M4 D4/AD4 L5 I/O, tri-state D3/AD3 K7 D2/AD2 P4 D1/AD1 M5 D0/AD0 L6 A5/BSWP N10 OE R12 I CLKE/MUX T14 ...
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NAME PIN TYPE I, RSTB B5 pullup H8, DVDD I J9 H9, DVSS I J8 VDDT1 D1 VDDT2 G1 VDDT3 J1 VDDT4 M1 VDDT5 T4 VDDT6 T7 VDDT7 T9 VDDT8 T12 I, high-Z VDDT9 N16 VDDT10 K16 VDDT11 H16 VDDT12 ...
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FUNCTIONAL DESCRIPTION 5.1 Port Operation 5.1.1 Serial Port Operation Setting MODESEL = ‘low’ enables the serial bus interface on the DS26324. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by ...
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Figure 5-3. Serial Port Operation for Read Access with CLKE = 1 SCLK CSB SDI (lsb) SDO 5.1.2 Parallel Port Operation When using the parallel interface on the DS26324 the user has ...
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Figure 5-4. Interrupt Handling Flow Diagram 5.2 Power-Up and Reset Internal Power_On_Reset circuitry generates a reset during power-up. All registers are reset to the default values. Writing to the Software Reset Register generates at least 1µs reset cycle, which has ...
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Figure 5-5. Prescaler PLL and Clock Generator MPS1..0 FREQS Pre MCLK Scaler PLL 5.4 Transmitter NRZ data arrives on TPOS and TNEG on the transmit system side. The TPOS and TNEG data is sampled on the falling edge of TCLK. ...
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Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters TRANSMITTER FUNCTION AMI Coding, B8ZS Substitution, DS1 Electrical Interface T1 Telecom Pulse Mask compliance T1 Telecom Pulse Mask compliance Transmit Electrical Characteristics for E1 Transmission and Return Loss Compliance Table 5-3. Registers ...
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Transmit Line Templates The DS26324 transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1 pulse mask is shown in the Transmit Pulse Template and can be configured on an individual LIU ...
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Figure 5-6. T1 Transmit Pulse Templates ...
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Figure 5-7. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit 194ns 219ns -150 -100 - TIME (ns) ...
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LIU Transmit Front-End It is recommended that the LIU for the transmitter be configured as described in Figure 5-8. LIU Front-End 3.3V VDDTn TTIP C1 C2 GNDTn TRING (One Channel) 3.3V RTIP AVDDn C3 C4 A75 AVSSn RRING 3.3V ...
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Table 5-5. LIU Front-End Values MODE COMPONENT Tx Capacitance Tx Protection Rx Transformer RTR 1:1 Tx Transformer 1:2 Rx Transformer RTR 1:2 Tx Transformer 1:2 Tx Decoupling (TVDDn) Tx Decoupling (TVDDn) Rx Decoupling (AVDD) Rx Decoupling (AVDD) Rx Termination Rx ...
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Transmit All Ones When Transmit All Ones is invoked, continuous ones are transmitted using MCLK as the timing reference. Data input at TPOS and TNEG is ignored. Transmit All Ones can be sent by setting bits in the in ...
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Peak Detector and Slicer The slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock and data recovery circuitry for extraction of data and clock. The slicer has a ...
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ANSI T1.231 for T1 and J1 Modes Loss is detected if the received signal level is less than 200mV for duration of 192 bit periods. LOS is reset if the all of the following criteria are met: • 24 ...
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The bipolar violation (and B8ZS/HDB3) detectors detect violations in dual-rail and single-rail modes, but in dual-rail mode the violations will only be reported to the Line Violation Detect Status (LVDS) registers. 5.5.9 Receive Single-Rail Mode Receive ...
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Jitter Attenuator The DS26324 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS bit in register GC. It can also be controlled on an individual LIU basis ...
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G.772 Monitor In this application, only 14 transceivers are functional and two transceivers are used for nonintrusive monitoring of input and output of the other 14 channels. Channel 9 is used for channels and Channel 1 ...
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Digital Loopback The transmit system data TPOS, TNEG, and TCLK will be looped back to output on RCLK, RPOS, and RNEG. The data input at TPOS and TNEG is output on TTIP and TRING. All ones can also be ...
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BERT There are two bit error-rate testers available on the DS26324. One BERT can be mapped into LIUs 1–8 and the other into LIUs 9–16 via the BTCR Each BERT transmitter, by default, replaces data from TPOS and TNEG; ...
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Configuration and Monitoring Set BTCR.BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send and receive common patterns. Table 5-11. Pseudorandom Pattern Generation PATTERN TYPE PTF[4:0] (hex ...
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Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) ...
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Receive Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the ...
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Transmit Pattern Generation Pattern generation generates the outgoing test pattern, and passes it onto error insertion. The transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the ...
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REGISTER MAPS AND DEFINITION Six address bits are used to control the settings of the registers. In the parallel nonmultiplexed mode address [5:0] is used. In multiplexed mode AD[5:0] is used and A[6:1] is used in the serial mode. ...
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Table 6-1. Primary Register Set REGISTER Identification Analog Loopback Control Remote Loopback Control Transmit All Ones Enable Loss of Signal Status Driver Fault Monitor Status Loss of Signal Interrupt Enable Driver Fault Monitor Interrupt Enable Loss of Signal Interrupt Status ...
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Table 6-2. Secondary Register Set REGISTER Single-Rail Mode Select Line Code Selection Not Used Receive Power-Down Enable Transmit Power-Down Enable Excessive Zero Detect Enable Code Violation Detect Enable Bar Not Used Address Pointer for Bank Selection DS26324 3.3V, 16-Channel, E1/T1/J1 ...
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Table 6-3. Individual LIU Register Set REGISTER NAME Individual Jitter Attenuator Enable IJAE Individual Jitter Attenuator Position IJAPS Select Individual Jitter Attenuator FIFO IJAFDS Depth Select Individual Jitter Attenuator FIFO IJAFLT Limit Trip Individual Short-Circuit Protection ISCPD Disable Individual AIS ...
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Table 6-4. BERT Register Set REGISTER BERT Control Reserved BERT Pattern Configuration 1 BERT Pattern Configuration 2 BERT Seed/Pattern 1 BERT Seed/Pattern 2 BERT Seed/Pattern 3 BERT Seed/Pattern 4 Transmit Error Insertion Control Reserved BERT Status Reserved BERT Status Register ...
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Table 6-5. Primary Register Set Bit Map ADDRESS FOR LIUs REGISTER R/W BIT 7 1– ID7 ALBC 01 RW ALBC8 RLBC 02 RW RLBC8 TAOE 03 RW TAOE8 LOSS 04 RW LOSS8 DFMS 05 RW DFMS8 LOSIE ...
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Table 6-6. Secondary Register Set Bit Map ADDRESS FOR LIUs REGISTER RW 1–8 SRMS 00 RW SRMS8 LCS 01 RW Not Used 02 RW RPDE 03 RW RPDE8 TPDE 04 RW TPDE8 EZDE 05 RW EZDE8 CVDEB 06 RW CVDEB8 ...
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Table 6-7. Individual LIU Register Set Bit Map ADDRESS FOR LIUs REGISTER RW BIT 7 1–8 IJAE 00 RW IJAE8 IJAPS 01 RW IJAPS8 IJAFDS 02 RW IJAFDS8 IJAFLT 03 R IJAFLT8 ISCPD 04 RW ISCPD8 IAISEL 05 RW IAISEL8 ...
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Table 6-8. BERT Register Bit Map ADDRESS FOR LIUs REGISTER RW 1–8 9–16 BCR Not Used 01 21 — BPCR1 BPCR2 03 23 — BSPR1 BSPR2 05 25 — BSPR3 06 ...
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Register Description This section contains the detailed register descriptions of each bit. Whenever the variable “n” in italics is used in any of the register descriptions, it represents 1–16. Note that in the register descriptions, there are duplicate registers ...
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RLBC Register Name: Remote Loopback Control Register Description: 02h Register Address (LIUs 1–8): Bit # 7 6 Name RLBC8 RLBC7 Default 0 0 Register Address (LIUs 9–16): 22h Bit # 7 6 Name RLBC16 RLBC15 Default 0 0 Bits 7 ...
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DFMS Register Name: Driver Fault Monitor Status Register Description: 05h Register Address (LIUs 1–8): Bit # 7 6 Name DFMS8 DFMS7 Default 0 0 Register Address (LIUs 9–16): 25h Bit # 7 6 Name DFMS16 DFMS15 Default 0 0 Bits ...
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LOSIS Register Name: Loss of Signal Interrupt Status Register Description: 08h Register Address (LIUs 1–8): Bit # 7 6 Name LOSIS8 LOSIS7 Default 0 0 Register Address (LIUs 9–16): 28h Bit # 7 6 Name LOSIS16 LOSIS15 Default 0 0 ...
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SWR Register Name: Software Reset Register Description: 0Ah Register Address (LIUs 1–8): Bit # 7 6 Name SWRL SWRL Default 0 0 Bits Software Reset (SWRL). Whenever any write is performed to this register, at least 1µs ...
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BGMC Register Name: BERT and G.772 Monitoring Control Register Description: 0Bh Register Address (LIUs 1–8): Bit # 7 6 Name BERTDIR BMCKS Default 0 0 Bit 7: BERT Direction Control Bit (BERTDIR). When this bit is set, the BERT for ...
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Table 6-9. G.772 Monitoring Control (LIU 1) GMC3 GMC2 GMC1 ...
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DLBC Register Name: Digital Loopback Control Register Description: 0Ch Register Address (LIUs 1–8): Bit # 7 6 Name DLBC8 DLBC7 Default 0 0 Register Address (LIUs 9–16): 2Ch Bit # 7 6 Name DLBC16 DLBC15 Default 0 0 Bits 7 ...
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GC Register Name: Global Configuration Register Description: 0Fh Register Address (LIUs 1–8): Bit # 7 6 Name RIMPMS AISEL Default 0 0 Note: CRIMP controls all 16 LIUs. All other bits are for LIUs 1–8 only. Bit 7: Receive Impedance ...
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Register Address (LIUs 9–16): Bit # 7 6 Name RIMPMS AISEL Default 0 0 Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the fully internal receive impedance matching mode is selected, so RTIP and RRING ...
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TST Register Name: Template Select Transmitter Register Description: 10h Register Address (LIUs 1–8): Bit # 7 6 Name JABWS1 JABWS0 Default 0 0 Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to ...
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Table 6-11. TST Template Select Transmitter Register (LIUs 1–8) TST[2:0] CHANNEL 000 1 001 2 010 3 011 4 Table 6-12. TST Template Select Transmitter Register (LIUs 9–16) TST[2:0] CHANNEL 000 9 001 10 010 11 011 12 DS26324 3.3V, ...
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TS Register Name: Template Select Register Description: 11h Register Address (LIUs 1–8): 31h Register Address (LIUs 9–16): Bit # 7 6 Name RIMPON TIMPOFF Default 0 0 Note: This register configures each LIU individually. This register configures the LIU selected ...
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OE Register Name: Output Enable Configuration Register Description: 12h Register Address (LIUs 1–8): Bit # 7 6 Name OE8 OE7 Default 0 0 Register Address (LIUs 9–16): 32h Bit # 7 6 Name OE16 OE15 Default 0 0 Bits 7 ...
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AISIE Register Name: AIS Interrupt Enable Register Description: 14h Register Address (LIUs 1–8): Bit # 7 6 Name AISIE8 AISIE7 Default 0 0 Register Address (LIUs 9–16): 34h Bit # 7 6 Name AISIE16 AISIE15 Default 0 0 Bits 7 ...
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ADDP Register Name: Address Pointer for Bank Selection Register Description: 1Fh Register Address (LIUs 1–8): 3Fh Register Address (LIUs 9–16): Bit # 7 6 Name ADDP7 ADDP6 Default 0 0 Bits Address Pointer (ADDP). This pointer is ...
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LCS Register Name: Line Code Selection Register Description: 01h Register Address (LIUs 1–8): Bit # 7 6 Name LCS8 LCS7 Default 0 0 Register Address (LIUs 9–16): 21h Bit # 7 6 Name LCS16 LCS15 Default 0 0 Bits 7 ...
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EZDE Register Name: Excessive Zero Detect Enable Register Description: 05h Register Address (LIUs 1–8): Bit # 7 6 Name EZDE8 EZDE7 Default 0 0 Register Address (LIUs 9–16): 25h Bit # 7 6 Name EZDE16 EZDE15 Default 0 0 Bits ...
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Individual LIU Register Bank The ADDP register must be set to 01h to access this bank. Register Name: IJAE Register Description: Individual Jitter Attenuator Enable Register Address (LIUs 1–8): 00h Bit # 7 6 Name IJAE8 IJAE7 Default 0 ...
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IJAFDS Register Name: Individual Jitter Attenuator FIFO Depth Select Register Description: 02h Register Address (LIUs 1–8): Bit # 7 6 Name IJAFDS8 IJAFDS7 Default 0 0 Register Address (LIUs 9–16): 22h Bit # 7 6 Name IJAFDS16 IJAFDS15 Default 0 ...
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IAISEL Register Name: Individual AIS Select Register Description: 05h Register Address (LIUs 1–8): Bit # 7 6 Name IAISEL8 IAISEL7 Default 0 0 Register Address (LIUs 9–16): 25h Bit # 7 6 Name IAISEL16 IAISEL15 Default 0 0 Bits 7 ...
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MC Register Name: Master Clock Select Register Description: 06h Register Address: Bit # 7 6 Name PCLKI1 PCLKI0 Default 0 0 Bits 7 and 6: PLL Clock Input [1:0] (PCLKI[1:0]). These bits select the input into to the PLL. 00: ...
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RSMM1 Register Name: Receive Sensitivity Monitor Mode 1 Register Description: 08h Register Address (LIUs 1–8): Bit # 7 6 Name RTR2 C2RSM2 Default 0 0 Bit 7: Receiver Transformer Turns Ratio Channel 2 (RTR2). If this bit is set the ...
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RSMM2 Register Name: Receive Sensitivity Monitor Mode 2 Register Description: 09h Register Address (LIUs 1–8): Bit # 7 6 Name RTR4 C4RSM2 Default 0 0 Bit 7: Receiver Transformer Turns Ratio Channel 4 (RTR4). If this bit is set the ...
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RSMM3 Register Name: Receive Sensitivity Monitor Mode 3 Register Description: 0Ah Register Address (LIUs 1–8): Bit # 7 6 Name RTR6 C6RSM2 Default 0 0 Bit 7: Receiver Transformer Turns Ratio Channel 6 (RTR6). If this bit is set the ...
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RSMM4 Register Name: Receive Sensitivity Monitor Mode 4 Register Description: 0Bh Register Address (LIUs 1–8): Bit # 7 6 Name RTR8 C8RSM2 Default 0 0 Bit 7: Receiver Transformer Turns Ratio Channel 8 (RTR8). If this bit is set the ...
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RSL1 Register Name: Receive Signal Level Indicator 1 Register Description: 0Ch Register Address (LIUs 1–8): Bit # 7 6 Name C2RSL3 C2RSL2 Default 0 0 Bits Channel 2 Receive Signal Level [3:0] (C2RSL[3:0]). C2RSL[3:0] bits provide the ...
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Table 6-17. Receiver Signal Level CnRSL3 to RECEIVE LEVEL (dB) CnRSL0 T1 0000 >-2.5 0001 -2 0010 -5 to -7.5 0011 -7.5 to -10 0100 -10 to -12.5 0101 -12.5 to -15 0110 -15 to -17.5 0111 -17.5 ...
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RSL3 Register Name: Receive Signal Level Indicator 3 Register Description: 0Eh Register Address (LIUs 1–8): Bit # 7 6 Name C6RSL3 C6RSL2 Default 0 0 Bits Channel 6 Receive Signal Level [3:0] (C6RSL[3:0]). C6RSL[3:0] bits provide the ...
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RSL4 Register Name: Receive Signal Level Indicator 4 Register Description: 0Fh Register Address (LIUs 1–8): Bit # 7 6 Name C8RSL3 C8RSL2 Default 0 0 Bits Channel 8 Receive Signal Level [3:0] (C8RSL[3:0]). C8RSL[3:0] bits provide the ...
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BTCR Register Name: Bit Error Rate Tester Control Register Description: 10h Register Address (LIUs 1–8): Bit # 7 6 Name BTS2 BTS1 Default 0 0 Note: This register enables the LIU1-LIU8 BERT. The BERT can only connect to one LIU ...
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Table 6-18. Bit Error Rate Transceiver Select for Channels 1–8 REGISTER BTS2 ADDRESS 10h 0 10h 0 10h 0 10h 0 10h 1 10h 1 10h 1 10h 1 Table 6-19. Bit Error Rate Transceiver Select for Channels 9–16 REGISTER ...
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LVDS Register Name: Line Violation Detect Status Register Description: 12h Register Address (LIUs 1–8): Bit # 7 6 Name LVDS8 LVDS7 Default 0 0 32h Register Address (LIUs 9–16): Bit # 7 6 Name LVDS16 LVDS15 Default 0 0 Bits ...
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TCLKI Register Name: Transmit Clock Invert Register Description: 14h Register Address (LIUs 1–8): Bit # 7 6 Name TCLKI8 TCLKI7 Default 0 0 Register Address (LIUs 9–16): 34h Bit # 7 6 Name TCLKI16 TCLKI15 Default 0 0 Bits 7 ...
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CCR Register Name: Clock Control Register Description: 15h Register Address: Bit # 7 6 Name PCLKS2 PCLKS1 Default 0 0 Bits PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that used as the ...
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RDULR Register Name: RCLK Disable Upon LOS Register Description: 16h Register Address (LIUs 1–8): Bit # 7 6 Name RDULR8 RDULR7 Default 0 0 Register Address (LIUs 9–16): 36h Bit # 7 6 Name RDULR16 RDULR15 Default 0 0 Bits ...
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BERT Registers Register Name: BCR BERT Control Register Description: 00h Register Address (LIUs 1–8): 20h Register Address (LIUs 9–16): Bit # 7 6 Name PMUM LPMU Default 0 0 Bit 7: Performance Monitoring Update Mode (PMUM). When 0, a ...
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BPCR1 Register Name: BERT Pattern Configuration Register 1 Register Description: 02h Register Address (LIUs 1–8): 22h Register Address (LIUs 9–16): Bit # 7 6 Name — QRSS Default 0 0 Bit 6: QRSS Enable (QRSS). When 0, the pattern generator ...
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BSPR1 Register Name: BERT Seed/Pattern Register 1 Register Description: 04h Register Address (LIUs 1–8): 24h Register Address (LIUs 9–16): Bit # 7 6 Name BSP7 BSP6 Default 0 0 Register Name: BSPR2 Register Description: BERT Seed/Pattern Register 2 Register Address ...
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TEICR Register Name: Transmit Error Insertion Control Register Register Description: 08h Register Address (LIUs 1–8): 28h Register Address (LIUs 9–16): Bit # 7 6 Name — — Default 0 0 Bits Transmit Error Insertion Rate (TEIR[2:0]). These ...
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BSRL Register Name: BERT Status Register Latched Register Description: 0Eh Register Address (LIUs 1–8): 2Eh Register Address (LIUs 9–16): Bit # 7 6 Name — — Default 0 0 Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is ...
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RBECR1 Register Name: Receive BERT Bit Error Count Register 1 Register Description: 14h Register Address (LIUs 1–8): 34h Register Address (LIUs 9–16): Bit # 7 6 Name BEC7 BEC6 Default 0 0 Register Name: RBECR2 Register Description: Receive BERT Bit ...
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RBCR1 Register Name: Receive BERT Bit Count Register 1 Register Description: 18h Register Address (LIUs 1–8): 38h Register Address (LIUs 9–16): Bit # 7 6 Name BC7 BC6 Default 0 0 Register Name: RBCR2 Register Description: Receive BERT Bit Count ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26324 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26324 contains the following as required by ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCLK. The state diagram is shown in Figure 7-2. 7.1.1 Test-Logic-Reset Upon power-up, the ...
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Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With TMS LOW, a rising edge on TCLK moves the controller into the Capture-IR state and will initiate a scan sequence for ...
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Figure 7-2. TAP Controller State Diagram Test Logic 1 Reset 0 Run Test/ 0 Idle DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit 1 1 Select DR-Scan Capture DR Capture IR 0 Shift ...
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Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between TDI ...
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Table 7-2. ID Code Structure MSB Version Device ID Contact Factory 4 bits 16 bits Table 7-3. Device ID Codes DEVICE 16-BIT ID DS26324 003Ch 7.3 Test Registers IEEE 1149.1 requires a minimum of two test registers: the Bypass Register ...
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DC ELECTRICAL CHARACTERIZATION ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage (V ) Range with Respect Operating Temperature Range for DS26324G………………………………………………………………..0°C to +70°C Operating Temperature Range for DS26324GN………………………………………………..…………..-40°C to +85°C ...
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AC TIMING CHARACTERISTICS 9.1 Line Interface Characteristics Table 9-1. Transmitter Characteristics PARAMETER E1 75Ω E1 120Ω Output Mark Amplitude T1 100Ω T1 110Ω Output Zero Amplitude Transmit Amplitude Variation with Supply Single-Rail Transmit Path Delay Dual-Rail Table 9-2. Receiver ...
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Parallel Host Interface Timing Characteristics The following tables show the AC characteristics for the external bus interface. Table 9-3. Intel Read Mode Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD J SIGNAL SYMBOL ...
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Figure 9-1. Intel Nonmuxed Read Cycle CSB RDB ALE=(1) t13 A[5:0] D[7:0] RDYB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t2 t1 ADDRESS t6 DATA OUT t8 t15 100 of 120 t14 ...
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Figure 9-2. Intel Mux Read Cycle CSB RDB t11 ALE t4 AD[7:0] ADDRESS RDYB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t2 t1 t12 t6 t10 DATA OUT t8 t15 101 of 120 t14 ...
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Table 9-4. Intel Write Cycle Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD J SIGNAL SYMBOL NAME(S) WRB t1 Pulse width CSB t2 Setup time to WRB CSB t3 Hold time to WRB AD[7:0] ...
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Figure 9-3. Intel Nonmux Write Cycle CSB WRB ALE=(1) A[5:0] D[7:0] RDYB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t2 t1 t14 ADDRESS t6 WRITE DATA t8 t9 103 of 120 t5 t10 ...
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Figure 9-4. Intel Mux Write Cycle CSB WRB t12 ALE t4 AD[7:0] ADDRESS RDYB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t2 t1 t13 t8 t9 104 of 120 WRITE DATA t11 t10 ...
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Table 9-5. Motorola Read Cycle Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD J SIGNAL SYMBOL NAME(S) DSB t1 Pulse width CSB t2 Setup time to DSB active CSB t3 Hold time from DSB ...
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Figure 9-5. Motorola Nonmux Read Cycle CSB RWB DSB ASB=(1) t16 A[5:0] D[7:0] ACKB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit ADDRESS t8 t13 t14 106 of 120 t3 t5 t15 t10 DATA OUT t11 t12 ...
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Figure 9-6. Motorola Mux Read Cycle CSB t4 RWB DSB ASB t6 AD[7:0] ADDRESS ACKB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t2 t1 t14 t7 t8 DATA OUT t13 t14 107 of 120 t3 t5 t10 t11 t12 ...
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Table 9-6. Motorola Write Cycle Characteristics (V = 3.3V ±5 -40°C to +125°C.) (Note 1) (See DD J SIGNAL SYMBOL NAME(S) DSB t1 Pulse width CSB t2 Setup time to DSB active CSB t3 Hold time from DSB ...
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Figure 9-7. Motorola Nonmux Write Cycle CSB t4 RWB DSB ASB=(1) t10 A[5:0] D[7:0] ACKB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t2 t1 ADDRESS t13 t14 109 of 120 t3 t5 t15 t8 t9 WRITE DATA t11 t12 ...
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Figure 9-8. Motorola Mux Write Cycle CSB RWB DSB ASB AD[7:0] ADDRESS ACKB DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit t13 t14 110 of 120 t3 t5 t13 t9 WRITE DATA t12 t11 ...
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Serial Port Table 9-7. Serial Port Timing Characteristics (See Figure 9-9, Figure 9-10, and Figure PARAMETER SCLK High Time SCLK Low Time Active CSB to SCLK Setup Time Last SCLK to CSB Inactive Time CSB Idle Time SDI to ...
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System Timing Table 9-8. Transmitter System Timing (See Figure 9-12.) PARAMETER TPOS, TNEG Setup Time with Respect to TCLK Falling Edge TPOS, TNEG Hold Time with Respect to TCLK Falling Edge TCLK Pulse-Width High TCLK Pulse-Width Low TCLK Period ...
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Table 9-9. Receiver System Timing (See Figure 9-13.) PARAMETER Delay RCLK to RPOS, RNEG Valid Delay RCLK to CV Valid in Single-Rail Mode RCLK Pulse-Width High RCLK Pulse-Width Low RCLK Period Figure 9-13. Receiver Systems Timing 1 RCLK 2 RCLK ...
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JTAG Timing Table 9-10. JTAG Timing Characteristics (See Figure 9-14.) PARAMETER TCK Period TMS and TDI Setup to TCK TMS and TDI Hold to TCK TCK to TDO Hold Figure 9-14. JTAG Timing TCK t2 TMS TDI TDO DS26324 ...
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PIN CONFIGURATION Figure 10-1. 256-Ball TE-CSBGA RTIP1 RRING1 MODESEL RTIP16 B AVDD AVSS MOTEL RRING16 C RTIP2 RRING2 TNEG1 A4 D VDDT1 LOS1 RCLK1 GNDT1 E TTIP1 TRING1 RNEG1 A5 F TTIP2 TRING2 RPOS2 ...
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PACKAGE INFORMATION For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but ...
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THERMAL INFORMATION Table 12-1. Thermal Characteristics PARAMETER Ambient Temperature Junction Temperature Theta-JA (θ Still Air Conduction JA Theta-JC (θ ) Conduction JC Theta-JB (θ ) Conduction JB Theta-JA (θ Forced Air JA Theta-JA (θ ) ...
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Table 12-3. Per-Channel Power-Down Savings (for Thermal Considerations) TYPICAL 50% 1s (Note 1) MODE FULLY PARTIALLY INTERNAL INTERNAL 0.093 0.080 E1-75Ω 0.084 0.065 E1-120Ω T1-LBO0 0.108 0.086 T1-LBO1 0.111 0.089 T1-LBO2 0.113 0.091 T1-LBO3 0.115 0.093 T1-LBO4 0.117 0.095 J1-LBO0 ...
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DATA SHEET REVISION HISTORY REVISION DATE Initial release. 070105 Added descriptions of feature enhancements implemented in revision A2: 1) Programmable corner frequency for the jitter attenuator in E1 mode. 2) Fully internal impedance matching option for RTIP/RRING. 3) Option ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time © 2011 Maxim Integrated Products DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc. 120 of 120 PAGES CHANGED 53 56 ...