RC48F4400P0TB0EA Micron Technology Inc, RC48F4400P0TB0EA Datasheet

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RC48F4400P0TB0EA

Manufacturer Part Number
RC48F4400P0TB0EA
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of RC48F4400P0TB0EA

Cell Type
NOR
Density
512Mb
Interface Type
Parallel/Serial
Boot Type
Bottom
Address Bus
25b
Operating Supply Voltage (typ)
2.5/3/3.3V
Operating Temp Range
-40C to 85C
Package Type
EZBGA
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
32M
Supply Current
31mA
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant
Numonyx
65nm)
256-Mbit, 512-Mbit (256M/256M)
Product Features
Datasheet
1
High performance:
— 95ns initial access time for Easy BGA
— 105ns initial access time for TSOP
— 25ns 16-word asynchronous-page read
— 52MHz (Easy BGA) with zero wait states,
— 4-, 8-, 16-, and continuous-word options
— Buffered Enhanced Factory Programming at
— 3.0V buffered programming at 1.14 MByte/
Architecture:
— Multi-Level Cell Technology: Highest
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
— 128-KByte main blocks
— Blank Check to verify an erase block
Voltage and Power:
— V
— V
— Standby current: 65uA (Typ) for 256-Mbit
— Continuous synchronous read current: 21
mode
17ns clock-to-data output synchronous-
burst read mode
for burst mode
2.0MByte/s (typ) using 512-word buffer
s (Typ) using 512-word buffer
Density at Lowest Cost
bottom configuration
mA (Typ)/24 mA (Max) at 52 MHz
CC
CCQ
(core) voltage: 2.3 V – 3.6 V
(I/O) voltage: 2.3 V – 3.6 V
®
Axcell
TM
Flash Memory (P33-
Security:
— One-Time Programmable Registers:
— Absolute write protection: V
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down capability
— Password Access feature
Software:
— 25µs (Typ) program suspend
— 25µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
— Common Flash Interface capable
Density and Packaging
— 56-Lead TSOP package (256-Mbit only)
— 64-Ball Easy BGA package (256, 512-Mbit)
— 16-bit wide data bus
Quality and Reliability
— JESD47E Compliant
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— 65nm ETOX™ X process technology
— 64 unique factory device identifier bits
— 2112 user-programmable OTP bits
Interface Command Set compatible
Order Number: 320003-09
PP
Datasheet
= V
SS
Mar 2010

Related parts for RC48F4400P0TB0EA

RC48F4400P0TB0EA Summary of contents

Page 1

... Password Access feature Software: — 25µs (Typ) program suspend — 25µs (Typ) erase suspend — Numonyx™ Flash Data Integrator optimized — Basic Command Set and Extended Function Interface Command Set compatible — Common Flash Interface capable Density and Packaging — ...

Page 2

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal Lines and Disclaimers OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS ...

Page 3

P33-65nm Contents 1.0 Functional Description ............................................................................................... 5 1.1 Introduction ....................................................................................................... 5 1.2 Overview ........................................................................................................... 5 1.3 Virtual Chip Enable Description.............................................................................. 6 1.4 Memory Maps ..................................................................................................... 7 2.0 Package Information ................................................................................................. 8 2.1 56-Lead TSOP..................................................................................................... 8 2.2 64-Ball Easy BGA Package ...

Page 4

... AC Write Specifications .......................................................................................54 15.5 Program and Erase Characteristics .......................................................................58 16.0 Ordering Information...............................................................................................59 16.1 Discrete Products...............................................................................................59 16.2 SCSP Products...................................................................................................60 A Supplemental Reference Information.......................................................................61 A.1 Common Flash Interface .....................................................................................61 A.2 Flowcharts ........................................................................................................72 A.3 Write State Machine ...........................................................................................81 B Conventions - Additional Documentation .................................................................87 B.1 Acronyms .........................................................................................................87 B.2 Definitions and Terms ........................................................................................87 C Revision History ...

Page 5

... The P33 Family Flash memory one-time-programmable (OTP) register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. The P33-65nm device adds enhanced protection via Password Access Mode which allows user to protect write and/or read access to the defined blocks ...

Page 6

... When chip enable is asserted and A25 is low ( parameter die is selected; when chip enable is asserted and A25 is high ( upper parameter die is selected. Table 1: Flash Die Virtual Chip Enable Truth Table for 512 Mbit Easy BGA Package Die Selected Lower Param Die Upper Param Die ...

Page 7

P33-65nm 1.4 Memory Maps Figure 1: P33-65nm Memory Map A<24:1 > 256 Mbit : 64- Kword Block FF 0000 - FFFFFF 64- Kword Block 7F 0000 - 7FFFFF 3 F0000 - 3FFFFF 64- Kword Block 020000 – 02 FFFF 64- ...

Page 8

Package Information 2.1 56-Lead TSOP Figure 2: TSOP Mechanical Specifications (256-Mbit) Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 2: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A ...

Page 9

P33-65nm Table 2: TSOP Package Dimensions (Sheet Product Information Symbol Lead Count N Lead Tip Angle θ Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes Pin ...

Page 10

... Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Note: Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology developer.numonyx.com/design/flash/packtech. Datasheet 10 Millimeters Symbol Min Nom Max ...

Page 11

... No Internal Connection on VCC Pin 13; it may be driven or floated. For legacy designs, pin can be tied to Vcc. 4. One dimple on package denotes Pin 1, which will always be in the upper left corner of the package, in reference to the product mark. Datasheet 11 ® Numonyx ™ Axcell Flash Memory (P33) 56-Lead TSOP Pinout Top View 56 WAIT A17 55 DQ15 54 ...

Page 12

Figure 5: 64-Ball Easy BGA Ballout (256-Mbit, 512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# VCCQ E DQ8 DQ1 DQ9 DQ3 F RFU ...

Page 13

... PPH cycles. VPP can be connected for a cumulative total not to exceed 80 hours. Extended use of this pin may reduce block cycling capability. DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when VCC ≤ V ...

Page 14

Table 4: TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and RFU — enhancement. These should be treated in the same way as a Don’t ...

Page 15

... Read To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. 5.2 ...

Page 16

... As with any automated device important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory the system boot device CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data ...

Page 17

... The on-chip WSM manages all block- erase and word-program algorithms. Device commands are written to the CUI to control all flash memory device operations. The CUI does not occupy an addressable memory location the mechanism through which the flash device is controlled ...

Page 18

Table 6: Command Codes and Definitions (Sheet Mode Code Device Mode Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Block lock Setup 0x01 Block lock Protection 0xD0 Unlock Block 0x2F Lock-Down Block Protection program 0xC0 ...

Page 19

P33-65nm Table 7: Command Bus Cycles (Sheet Mode Command Read Array Read Device Identifier Read Read CFI Read Status Register Clear Status Register Word Program (3) Buffered Program Program Buffered Enhanced Factory Program (4) (BEFP) Erase Block ...

Page 20

Table 7: Command Bus Cycles (Sheet Mode Command Blank Check Extended Function Others Interface (5) command Notes: 1. First command cycle address should be the same as the operation’s target address. DBA = Device Base Address (NOTE: ...

Page 21

... The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power- reset. The RCR must be configured to enable synchronous burst reads of the flash memory array (see 7.1 ...

Page 22

... The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by either of the 256-Mbit Device ID codes depending on its parameter option. 7.4 Read CFI The Read CFI command instructs the device to output Common Flash Interface data when read. Datasheet 22 Table 8, “ ...

Page 23

... The device features a 512-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. (see When the Buffered Programming Setup command is issued, Status Register information is updated and reflects the availability of the buffer ...

Page 24

... BEFP consists of three phases: Setup, Program/Verify, and Exit It uses a write buffer to spread MLC program performance across 512 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 512 data words. Host programmer bus cycles fill the device’ ...

Page 25

... BEFP cannot be suspended • Programming to the flash memory array can occur only when the buffer is full. If the number of words is less than 512, remaining locations must be filled with 0xFFFF. ...

Page 26

... Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 512, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately ...

Page 27

P33-65nm To read data from the device, the Read Array command must be issued. Read Array, Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid commands during a program suspend. During a program suspend, deasserting CE# ...

Page 28

... Erase Operation Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. ...

Page 29

P33-65nm The status register can be examined for Blank Check progress and errors by reading any address within the block being accessed. During a blank check operation, the Status Register indicates a busy status (SR.7 = 0). Upon completion, the ...

Page 30

... The following sections describe each security mode in detail. 10.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. ...

Page 31

P33-65nm 10.1.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 7.3, “Read Device Identifier” on page addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is ...

Page 32

If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See ...

Page 33

P33-65nm 11.0 Status Register To read the Status Register, issue the Read Status Register command at any address. Status Register information is available to which the Read Status Register, Word Program, or Block Erase command was issued. SRD is automatically ...

Page 34

Clear Status Register The Clear Status Register command clears the status register. It functions independent of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting ...

Page 35

P33-65nm Table 11: Read Configuration Register Description (Sheet Burst Wrap (BW) 3 2:0 Burst Length (BL[2:0]) 11.1.1 Read Mode The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM ...

Page 36

Figure 9: First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 DQ [D/Q] ...

Page 37

P33-65nm Figure 10: Example Latency Count Setting Using Code 3 CLK CE# ADV# A[MAX:0] A[MAX:1] D[15:0] 11.1.3 End of Word Line (EOWL) Considerations End of Wordline (EOWL) WAIT states can result when the starting address of the burst operation is ...

Page 38

Table 13: End of Wordline Data and WAIT state Comparison Latency Count Data States 1 Not Supported Not Supported 11.1.4 ...

Page 39

P33-65nm Table 14: WAIT Functionality Table Condition CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ CE# =’0’, OE# = ‘0’ Synchronous Array Reads Synchronous Non-Array Reads All Asynchronous Reads All Writes Notes: 1. Active: WAIT ...

Page 40

... Burst Length The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous burst accesses are linear only, and do not wrap within any word length ...

Page 41

P33-65nm The OTP Registers contain OTP bits; when programmed, PR bits cannot be erased. Each OTP Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each OTP Register has an associated Lock ...

Page 42

Programming the OTP Registers To program any of the OTP Registers, first issue the Program OTP Register command at the parameter’s base address plus the offset to the desired OTP Register (see 6.2, “Device Command Bus Cycles” on page ...

Page 43

... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...

Page 44

... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx MLC flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High- frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...

Page 45

P33-65nm 13.0 Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Table 17: Absolute Maximum Ratings Parameter Temperature under bias Storage temperature ...

Page 46

Electrical Specifications 14.1 DC Current Characteristics Table 19: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], WAIT LO Current 256-Mbit I , VCC Standby, CCS I Power-Down 512-Mbit CCD ...

Page 47

P33-65nm Table 19: DC Current Characteristics (Sheet Sym Parameter I VPP Blank Check PPBC Notes: 1. All currents are RMS unless noted. Typical values at typical VCC the average current measured over any ...

Page 48

AC Characteristics 15.1 AC Test Conditions Figure 14: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends ...

Page 49

P33-65nm 15.2 Capacitance Table 22: Capacitance Symbol Signal Input Address, Data, CE#, Capacita WE#, OE#, RST#, 256-Mbit/256Mbit nce CLK, ADV#, WP# Output Capacita Data, WAIT 256-Mbit/256Mbit nce Notes: 1. Sampled, not 100% tested. 15.3 AC Read Specifications Table 23: AC ...

Page 50

Table 23: AC Read Specifications - (Sheet Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to output valid VLQV R104 t ADV# pulse ...

Page 51

P33-65nm Table 23: AC Read Specifications - (Sheet Num Symbol (5) Synchronous Specifications R301 t Address setup to CLK AVCH/L R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 ...

Page 52

Figure 18: Asynchronous Single-Word Read (ADV# Latch) Address [A] A[1:0][A] R101 R105 R105 R106 ADV# CE# [E} OE# [G] R15 WAIT [T] Data [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low) Figure 19: Asynchronous Page-Mode ...

Page 53

... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Figure 21: Continuous Burst Read, showing an Output Delay Timing ...

Page 54

Figure 22: Synchronous Burst-Mode Four-Word Read Timing R302 R301 R306 CLK [C] R101 Address [A] A R105 R105 R106 R102 ADV# [V] R303 CE# [E] OE# [G] R15 WAIT [T] Data [D/Q] Note: WAIT is driven per OE# assertion during ...

Page 55

P33-65nm Table 24: AC Write Specifications (Sheet Num Symbol Write to Synchronous Read Specifications W19 t WE# high to Clock valid WHCH/L W20 t WE# high to ADV# high WHVH W28 t WE# high to ADV# low ...

Page 56

Figure 24: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] R5 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. ...

Page 57

P33-65nm Figure 26: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R105 R105 R106 R102 ADV# [V] R303 R3 CE# [E] OE# [G] WE# WAIT [T] Data [D/Q] Note: WAIT shown deasserted and High-Z per OE# ...

Page 58

Program and Erase Characteristics 15.5 Table 25: Program and Erase Specifications Num Symbol Parameter Program W200 t Single word PROG/W Time Aligned 32-Wd, BP time (32 Words) Aligned 64-Wd, BP time (64 Word) Program Aligned 128-Wd, BP time W250 t ...

Page 59

... -Lead TSOP , leaded JS = 56-Lead TSOP , lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free Product Line Designator 28F = Numonyx™ Flash Memory Device Density 256 = 256-Mbit Note: The last digit is randomly assigned to cover packing media and/or features or other specific configuration. Table 26: Valid Combinations for Discrete Products ...

Page 60

... SCSP Products Figure 29: Decoder for SCSP Devices Package Designator RC = 64- Ball Easy BGA, leaded PC = 64- Ball Easy BGA, lead - free Product Designator 48F = Numonyx™ Flash Memory Only Device Density die 4 = 256-Mbit Product Family ® Numonyx Axcell™ Flash Memory (P33) ...

Page 61

... The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. ...

Page 62

... A.1.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or database. locations. Table 30: Query Structure 00001-Fh Reserved 00010h CFI query identification string 0001Bh System interface information ...

Page 63

P33-65nm Table 31: CFI Identification Offset Length 10h 3 Query-unique ASCII string “QRY”. Primary Vendor command set and control interface ID code. 13h 2 16-bit ID code for Vendor-specified algorithms. 15h 2 Extended Query Table primay algorithm address. Alernate vendor ...

Page 64

... A.1.4 Device Geometry Definition Table 33: Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table 28h ...

Page 65

... BCD value in 100 mV bits 4–7 HEX value in volts A ddress Discrete –B –T –- –- die 1 (B) 112: --00 --00 Datasheet 65 Description (Optional flash features and com m ands) 512-Mbit –B –T die 2 (T) die 1 (T) die 2 (B) --40 --00 --40 --00 Hex Add. Code Value ...

Page 66

... Table 35: OTP Register Information Offset (1) Length P = 10Ah (Optional flash features and commands) (P+E)h 1 Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description (P+10)h This field describes user-available One Time Programmable (P+11)h (OTP) Protection register bytes ...

Page 67

... Datasheet 67 Description (Optional flash features and commands) n HEX value represents the number of Description (Optional flash features and commands) Hex Add. Code Value 127: --05 32 byte 128: --04 4 ...

Page 68

... Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+ (Type n blocks)x(Type n block sizes) Datasheet 68 Description (Optional flash features and commands) P33-65nm See table below Address Len Bot Top 2 ...

Page 69

... Reserved (P+38)h (P+38)h bits 32- Control Mode invalid size in bytes (P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) (P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information (P+3B)h (P+3B)h bits 0– y identical-size erase blks in a partition (P+3C)h (P+3C)h bits 16– ...

Page 70

Table 39: Partition and Erase Block Region Information Datasheet 70 Address 256-Mbit –B –T 12D: --01 --01 12E: --24 --24 12F: --00 --00 130: --01 --01 131: --00 --00 132: --11 --11 133: --00 --00 134: --00 --00 135: --02 ...

Page 71

... P33-65nm Table 40: CFI Link Information Length (Optional flash features and commands) 4 CFI Link Field bit definitions Bits 0–9 = Address offset (w ithin 32Mbit segment) of referenced CFI table Bits 10–27 = nth 32Mbit segment of referenced CFI table Bits 28–30 = Memory Type Bit 31 = Another CFI Link field immediately follow s ...

Page 72

A.2 Flowcharts Figure 31: Word Program Flowchart Start Command Cycle - Issue Program Command - Address = location to program - Data = 0x40 Data Cycle - Address = location to program - Data = Data to program Check Ready ...

Page 73

P33-65nm Figure 32: Program Suspend/Resume Flowchart Start Read Status Write 70h Any Address Program Suspend Write B0h Any Address Read Status Register Read Array Write FFh Any Address Read Array ...

Page 74

... Count ranges for this device are N=0000h to 00FFh. 2. The device outputs the status register when read. 3. Write Buffer contents will be programmed at the device start address or destination flash address . Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A Write Buffer Data 5 ...

Page 75

P33-65nm Figure 34: BEFP Flowchart Setup Phase Start Issue BEFP Setup Cmd (Data = 0x80) Issue BEFP Confirm Cmd (Data = 00D0h) BEFP Setup Delay Read Status Register Yes (SR.7=0) BEFP Setup Done ? No (SR.7=1) SR Error Handler (User-Defined) ...

Page 76

Figure 35: Block Erase Flowchart Start Command Cycle - Issue Erase command - Address = Block to be erased - Data = 0x20 Confirm Cycle - Issue Confirm command - Address = Block to be erased - Data = Erase ...

Page 77

P33-65nm Figure 36: Block Lock Operations Flowchart Start Lock Setup Write 60 h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90 h Read Block Lock Status Locking No Change ? Yes Read Array Write ...

Page 78

Figure 37: Erase Suspend/Resume Flowchart Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register SR SR Read Read or Program ? Read Array No Data Done? Yes Erase Resume ...

Page 79

P33-65nm Figure 38: OTP Register Programming Flowchart Datasheet 79 Start OTP Program Setup - Write 0xC0 - OTP Address Confirm Data - Write OTP Address and Data Check Ready Status - Read Status Register Command not required - Perform read ...

Page 80

Figure 39: Status Register Flowchart - Issue Status Register Command - Address = any device address - Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear ...

Page 81

P33-65nm A.3 Write State Machine Show here are the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read ...

Page 82

Table 41: Next State Table for P3x-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) Setup (8) BP Load 1 (8) BP Load 2 Buffer BP Confirm Ready (Error [Botch]) Pgm ...

Page 83

P33-65nm Table 41: Next State Table for P3x-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) EFI Setup Sub-function Setup Sub-op-code Sub-function Load 2 in Erase Suspend if word count >0, ...

Page 84

Table 42: Output Next State Table for P3x-65nm Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP Setup, Load 1, Load 2 BP Setup, ...

Page 85

... V (core) and V (I/O) voltage range of 2.3 V – 3 CCQ VPP voltage range of 8.5 V – 9 group of bits, bytes, or words within the flash memory array that erase simultaneously. The P33-65nm has two block sizes: 32 KByte and 128 KByte. Mar 2010 Order Number:320003-09 ...

Page 86

Main block : Parameter block : Top parameter device : Bottom parameter device : Datasheet 86 An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. An array block that may ...

Page 87

... Table CLK CLK CHQV CHTV . Figure 33 undershoot and overshoot of Note Section A.1, “Common Flash Interface” Figure 1, “P33-65nm Memory Map” signal naming and remove invalid x8 information Section 7.1, “Asynchronous Page-Mode . Table 19, “DC Current Characteristics” on page 46 on PPH TM trademark; ...

Page 88

Datasheet 88 P33-65nm Mar 2010 Order Number: 320003-09 ...

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