LMX3161VBH National Semiconductor, LMX3161VBH Datasheet
LMX3161VBH
Specifications of LMX3161VBH
Available stocks
Related parts for LMX3161VBH
LMX3161VBH Summary of contents
Page 1
... Block Diagram MICROWIRE ™ trademark of National Semiconductor Corporation. TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS012815 PRELIMINARY vides a low cost, high performance solution for communica- tions systems. The RSSI output may be used for channel quality monitoring. ...
Page 2
... LMX3161 Pin Diagram Order Number LMX3161VBH or LMX3161VBHX www.national.com Top View See NS Package Number VBH48A 2 DS012815-2 ...
Page 3
LMX3161 Pin Diagram (Continued) Pin No. Pin Name I — Power supply for CMOS section of PLL and ESD bussing MIXER O IF output from the mixer. OUT 3 V — Power supply for mixer section. ...
Page 4
LMX3161 Pin Diagram (Continued) Pin No. Pin Name I/O 42 LIM I IF input to the limiter GND — Ground output from IF amplifier. OUT 45 V — Power supply for IF amplifier output. ...
Page 5
Absolute Maximum Ratings Power Supply Voltage ( Voltage on Any Pin with GND = −0. Storage Temperature Range ( Lead Temp. (solder, 4 sec)( Electrical Characteristics ...
Page 6
Electrical Characteristics The following specifications are guaranteed for V Symbol Parameter RSSI (Note 11) RSSI Output Voltage out Slope RSSI Dynamic Range DC COMPENSATION CIRCUIT V Input Offset Voltage OS V Input/Output Voltage Swing I/O R Sample and Hold Resistor ...
Page 7
Electrical Characteristics Note 13: The doubler section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7 — 1.9 GHz range. Note 14: See Function Register Programming Description for Icp Note 15: Tested in a ...
Page 8
PLL Functional Description The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit data register, 18-bit F-latch, 12-bit N-counter, and 6-bit R-counter. The DATA stream is clocked into the data register ...
Page 9
Programmable Reference Divider (R-Counter) If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 6-bit R-counter. The serial data format is shown below. MSB ...
Page 10
Transmitter Functional Description The simplified block diagram below shows the doubler and voltage regulator for an external transmit gain stage. Note: The transmitter can be powered down, either by hardware through the Tx PD pin software through the ...
Page 11
Function Register Programming Description (F-Latch) Mode Control Model Control Description Bit F15 Demodulator DC level shift of 1.000V F16 Demodulator DC level shift of 0.500V F17 Demodulator DC level shift of 0.250V F18 Demodulator DC level shift of 0.125V Power ...
Page 12
Typical Application DECT System Calculation for 3.6V Operation Note: Assumes 50 dB attenuation of interferer by the SAW filter and 8 dB attenuation by the LC filter. Cascaded totals in Input IP3 are calculated at the output of the interstage ...
Page 13
Loop Filter Design Consideration FIGURE 1. Conventional PLL Architecture Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2 . The open loop gain is the ...
Page 14
... Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC Order Number LMX3161VBH or LMX3161VBHX LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION ...