ST62T65CN6 STMicroelectronics, ST62T65CN6 Datasheet - Page 11

• Manufacturer Part Number: ST62T65CN6
• Description: Microcontrollers (MCU) OTP EPROM 4K SPI
• Manufacturer: STMicroelectronics

Specifications of ST62T65CN6

• Processor Series: ST62T6x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Program Memory Size: 3884 B
• Data Ram Size: 128 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: Details

MEMORY MAP (Cont’d)
1.3.6
(DRBR)
Address: E8h — Write only
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3-2 - Reserved. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1, when available.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0, when available.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The bank number has to be loaded in
the DRBR register and the instruction has to point
to the selected location as if it was in bank 0 (from
00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
7
-
Data
-
RAM/EEPROM
-
DRBR
4
-
Bank
-
DRBR
1
Register
DRBR
0
0
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Care must also be taken not to change the
E²PROM page (when available) when the parallel
writing mode is set for the E²PROM, as defined in
EECTL register.
Table 3Data RAM Bank Register Set-up
DRBR
other
10h
00
01
02
08
Not Available
Not Available
Not Available
RAM Page 2
ST62T55C
ST62T55C ST62T65C/E65C
Reserved
None
EEPROM Page 0
EEPROM Page 1
ST62T65C/E65C
Not Available
RAM Page 2
Reserved
None
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