ST62T65CN6 STMicroelectronics, ST62T65CN6 Datasheet - Page 33

• Manufacturer Part Number: ST62T65CN6
• Description: Microcontrollers (MCU) OTP EPROM 4K SPI
• Manufacturer: STMicroelectronics

Specifications of ST62T65CN6

• Processor Series: ST62T6x
• Core: ST6
• Data Bus Width: 8 bit
• Program Memory Type: EPROM
• Program Memory Size: 3884 B
• Data Ram Size: 128 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: Details

INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused .
Bit 6 = LES: Level/Edge Selection bit .
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 9Interrupt Requests and Mask Bits
GENERAL
TIMER
A/D CONVERTER
AR TIMER
SPI
Port PAn
Port PBn
Port PCn
7
-
Peripheral
LES
ESB
GEN
IOR
TSCR1
ADCR
ARMC
SPIMOD
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
Register
-
-
C8h
D4h
D1h
D5h
E2h
C0h-C4h
C1h-C5h
C2h-C6h
Address
Register
-
0
-
GEN
ETI
EAI
OVIE
CPIE
EIE
SPIE
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
Mask bit
Bit 5 = ESB: Edge Selection bit .
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt . When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the
bit to enable/disable the interrupt request.
All Interrupts, excluding NM
TMZ: TIMER Overflow
EOC: End of Conversion
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
SPRUN: End of Transmission
PAn pin
PBn pin
PCn pin
Masked Interrupt Source
ST62T55C ST62T65C/E65C
Table 9
with associated mask
I
Vector 4
Vector 3
Vector 2
Vector 4
Vector 2
Vector 1
Vector 1
Interrupt
vector
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