ST72T631K4M1 STMicroelectronics, ST72T631K4M1 Datasheet
ST72T631K4M1
Specifications of ST72T631K4M1
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ST72T631K4M1 Summary of contents
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LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI Up to 16Kbytes program memory Data RAM 512 bytes with 64 bytes stack Run, Wait and Halt ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7263 7.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GENERAL DESCRIPTION 1.1 INTRODUCTION The ST7263 Microcontrollers form a sub family of the ST7 dedicated to USB applications. The de- vices are based on an industry-standard 8-bit core and feature an enhanced instruction set. They op- erate at a ...
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ST7263 1.2 PIN DESCRIPTION Figure 2. 34-Pin SO Package Pinout PC2/USBOE AIN7/IT8/PB7 (10mA) AIN6/IT7/PB6 (10mA) AIN5/IT6/PB5 (10mA) AIN4/IT5/PB4 (10mA) AIN3/PB3 (10mA) AIN2/PB2 (10mA) AIN1/PB1 (10mA EPROM/OTP versions only PP Figure 3. 32-Pin SDIP Package Pinout PC2/USBOE AIN7/IT8/PB7 ...
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PIN DESCRIPTION (Cont’d) RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered ...
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ST7263 Pin n° Pin Name 20 21 PA5/ICAP2/IT2 I PA4/ICAP1/IT1 I PA3/EXTCLK I PA2/SCL I PA1/SDA I PA0/MCO I/O ...
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EXTERNAL CONNECTIONS The following figure shows the recommended ex- ternal connections for the device. The V pin is only used for programming OTP PP and EPROM devices and must be tied to ground in user mode. The 10 nF ...
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ST7263 1.4 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 192 bytes of register location 512 bytes ...
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Table 4. Hardware Register Memory Map Address Block Register Label 0000h PADR 0001h PADDR 0002h PBDR 0003h PBDDR 0004h PCDR 0005h PCDDR 0006h 0007h 0008h ITIFRE 0009h MISCR 000Ah DR ADC 000Bh CSR 000Ch WDG CR 000Dh 0010h 0011h CR2 ...
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ST7263 Address Block Register Label 0025h PIDR 0026h DMAR 0027h IDR 0028h ISTR 0029h IMR 002Ah CTLR 002Bh USB DADDR 002Ch EP0RA 002Dh EP0RB 002Eh EP1RA 002Fh EP1RB 0030h EP2RA 0031h EP2RB 0032h 0038h 0039h 003Ah I ...
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... EPROM/OTP PROGRAM MEMORY The program memory of the ST72T63 may be pro- grammed using the EPROM programming boards available from STMicroelectronics (see 1.5.1 EPROM ERASURE ST72Exxx EPROM devices are erased by expo- sure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current ...
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ST7263 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two ...
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CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST7263 CPU REGISTERS (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 3Fh SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...
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CLOCKS AND RESET 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a Crystal or Ceramic res- onator external clock signal to drive the in- ternal oscillator. The internal clock (f rived from the external oscillator ...
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ST7263 3.2 RESET The Reset procedure is used to provide an orderly software start- exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external re- set at the ...
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Figure 11. Low Voltage Detector functional Diagram LOW VOLTAGE V DD DETECTOR FROM WATCHDOG RESET Figure 13. Temporization timing diagram after an internal Reset V DD Addresses Figure 14. Reset Timing Diagram t DDR V DD OSCIN t OXOV f ...
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ST7263 4 INTERRUPTS AND POWER SAVING MODES 4.1 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in Table 7 Interrupt Mapping maskable software interrupt (TRAP). The Interrupt processing flowchart ...
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INTERRUPTS (Cont’d) Figure 15. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 7. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt USB End Suspend Mode 1 ITi External Interrupts 2 TIMER Timer Peripheral Interrupts ...
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ST7263 INTERRUPTS (Cont’d) 4.1.1 Interrupt Register INTERRUPTS REGISTER (ITRFRE) Address: 0008h — Read/Write Reset Value: 0000 0000 (00h) 7 IT8E IT7E IT6E IT5E IT4E Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control Bits . 22/109 If an ITiE ...
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POWER SAVING MODES 4.2.1 Introduction To give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the ST7. After a RESET the normal operating mode ...
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ST7263 POWER SAVING MODES (Cont’d) 4.2.3 WAIT mode WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain ...
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ON-CHIP PERIPHERALS 5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – analog signal input (ADC) – alternate signal input/output for the on-chip ...
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ST7263 I/O PORTS (Cont’d) Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multi- plexer (controlled by the ADC registers) switches the analog voltage present on the ...
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I/O PORTS (Cont’d) 5.1.4 Port A Table 9. Port A0, A3, A4, A5, A6, A7 Description PORT A Input* PA0 with pull-up PA3 with pull-up PA4 with pull-up PA5 with pull-up PA6 with pull-up PA7 with pull-up *Reset State Figure ...
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ST7263 I/O PORTS (Cont’d) Table 10. PA1, PA2 Description PORT A Input* PA1 without pull-up PA2 without pull-up *Reset State Figure 19. PA1, PA2 Configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR SEL 28/109 Output ...
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I/O PORTS (Cont’d) 5.1.5 Port B Table 11. Port B Description PORT B Input* PB0 without pull-up PB1 without pull-up PB2 without pull-up PB3 without pull-up PB4 without pull-up PB5 without pull-up PB6 without pull-up PB7 without pull-up *Reset State ...
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ST7263 I/O PORTS (Cont’d) 5.1.6 Port C Table 12. Port C Description PORT C Input* PC0 with pull-up PC1 with pull-up PC2 with pull-up *Reset State Figure 21. Port C Configuration ALTERNATE OUTPUT DR LATCH DDR LATCH DDR SEL DR ...
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I/O PORTS (Cont’d) 5.1.7 Register Description DATA REGISTERS (PxDR) Port A Data Register (PADR): 0000h Port B Data Register (PBDR): 0002h Port C Data Register (PCDR): 0004h Read /Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: ...
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ST7263 5.2 MISCELLANEOUS REGISTER Address: 0009h — Read/Write Reset Value: 1111 0000 (F0h LVD Bit 7:4 = Reserved Bit 3 = LVD Low Voltage Detector. This bit is set by software and only cleared by ...
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WATCHDOG TIMER (WDG) 5.3.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its ...
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ST7263 WATCHDOG TIMER (Cont’d) 5.3.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. ...
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WATCHDOG TIMER (Cont’d) Table 15. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) WDGCR WDGA 0C Reset Value ST7263 ...
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ST7263 5.4 16-BIT TIMER 5.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input sig- nals ...
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TIMER (Cont’d) Figure 23. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT ST7 ...
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ST7263 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read Byte value at ...
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TIMER (Cont’d) Figure 24. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 25. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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ST7263 16-BIT TIMER (Cont’d) 5.4.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are ...
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TIMER (Cont’d) Figure 27. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 28. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive ...
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ST7263 16-BIT TIMER (Cont’d) 5.4.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform ...
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TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the bit is ...
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ST7263 16-BIT TIMER (Cont’d) Figure 30. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) Figure 31. Output Compare ...
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TIMER (Cont’d) 5.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input ...
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ST7263 16-BIT TIMER (Cont’d) Figure 32. One Pulse Mode Timing Example COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 33. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 ...
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TIMER (Cont’d) 5.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode ...
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ST7263 16-BIT TIMER (Cont’d) 5.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode ...
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TIMER (Cont’d) 5.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST7263 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST7263 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) ...
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TIMER (Cont’d) Table 17. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) CR2 OC1E 11 Reset Value 0 CR1 ICIE 12 Reset Value 0 SR ICF1 13 Reset Value 0 IC1HR 14 MSB Reset Value ...
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ST7263 5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 5.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. 5.5.2 Main Features Full duplex, asynchronous communications ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 34. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU /2 Read Received Data Register (RDR) Received Shift ...
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ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains 4 dedicated regis- ters: – Two control registers (CR1 & CR2) – A status register (SR) – ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the ...
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ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.4.4 Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (32 PR with ...
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ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. 5.5.6 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 5.5.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...
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ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received word ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs ...
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ST7263 SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 18. SCI Register Map and Reset Values Address Register (Hex.) Label 20 SR TDRE Reset Value 21 DR Reset Value 22 BRR SCP1 Reset Value 23 CR1 Reset Value 24 CR2 Reset Value 64/109 ...
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USB INTERFACE (USB) 5.6.1 Introduction The USB Interface implements a low-speed func- tion interface between the USB and the ST7 mi- crocontroller highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No ...
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ST7263 USB INTERFACE (Cont’d) 5.6.4 Register Description DMA ADDRESS REGISTER (DMAR) Read / Write Reset Value: Undefined 7 DA15 DA14 DA13 DA12 DA11 Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area ...
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USB INTERFACE (Cont’d) PID REGISTER (PIDR) Read only Reset Value: xx00 0000 (x0h) 7 TP3 TP2 Bits 7:6 = TP[3:2] Token PID bits 3 & USB token PIDs are encoded in four bits. TP[3:2] correspond ...
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ST7263 USB INTERFACE (Cont’d) Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software overrun detected 1: Overrun detected Bit 2 = ESUSP ...
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USB INTERFACE (Cont’d) DEVICE ADDRESS REGISTER (DADDR) Read / Write Reset Value: 0000 0000 (00h ADD6 ADD5 ADD4 ADD3 Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must ...
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ST7263 USB INTERFACE (Cont’d) ENDPOINT n REGISTER B (EPnRB) Read / Write Reset Value: 0000 xxxx (0xh) 7 DTOG STAT STAT CTRL _RX _RX1 _RX0 These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and ...
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USB INTERFACE (Cont’d) 5.6.5 Programming Considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with ...
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ST7263 USB INTERFACE (Cont’d) Table 19. USB Register Map and Reset Values Address Register 7 Name (Hex.) PIDR TP3 25 Reset Value x DMAR DA15 26 Reset Value x IDR DA7 27 Reset Value x ISTR SUSP 28 Reset Value ...
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I²C BUS INTERFACE (I²C) 5.7.1 Introduction The I²C Bus Interface serves as an interface be- tween the microcontroller and the serial I²C bus. It provides both multimaster and slave functions, and controls all I²C bus-specific sequencing, pro- tocol, arbitration ...
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ST7263 I²C BUS INTERFACE (Cont’d) The Acknowledge function may be enabled and disabled by software. The I²C interface address and/or general call ad- dress can be selected by software. The speed of the I²C interface may be selected be- tween ...
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I²C BUS INTERFACE (Cont’d) 5.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in 0.1.7. for the bit definitions. By default the I²C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit ...
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ST7263 I²C BUS INTERFACE (Cont’d) 5.7.4.2 Master Mode To switch from default Slave mode to Master mode, a Start condition generation is needed. Start Condition and Transmit Slave Address Setting the START bit while the BUSY bit is cleared causes ...
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I²C BUS INTERFACE (Cont’d) Figure 40. Transfer Sequencing Slave Receiver S Address A Data1 EV1 Slave Transmitter S Address A EV1 EV3 Master Receiver S Address A EV5 EV6 Master Transmitter S Address A EV5 EV6 EV8 Legend: S=Start, P=Stop, ...
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ST7263 I²C BUS INTERFACE (Cont’d) 5.7.5 Low Power Modes Mode Description No effect on I²C interface. WAIT I²C interrupts exit from Wait mode. I²C registers are frozen. In Halt mode, the I²C interface is inactive and does not acknowledge data ...
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I²C BUS INTERFACE (Cont’d) 5.7.7 Register Description I²C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK Bits 7:6 = Reserved. Forced hardware. Bit Peripheral ...
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ST7263 I²C BUS INTERFACE (Cont’d) I²C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF 0 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event ...
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I²C BUS INTERFACE (Cont’d) I²C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h STOPF ARLO BERR GCAL Bits 7:5 = Reserved. Forced hardware. Bit Acknowledge failure ...
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ST7263 I²C BUS INTERFACE (Cont’d) I²C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I²C mode. This bit is set and cleared by software. It ...
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Table 20 Register Map Address Register 7 Name (Hex OAR 3C CCR FM/SM 3D SR2 3E SR1 EVF DR7 .. DR0 ADD7 .. ADD0 CC6 .. CC0 AF STOPF ...
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ST7263 5.8 8-BIT A/D CONVERTER (ADC) 5.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels ...
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A/D CONVERTER (ADC) (Cont’d) 5.8.3 Functional Description The high level reference voltage V connected externally to the V DD reference voltage V must be connected exter- SSA nally to the V pin. In some devices (refer to de- SS ...
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ST7263 8-BIT A/D CONVERTER (ADC) (Cont’d) 5.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO - ADON 0 - Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by ...
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INSTRUCTION SET 6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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ST7263 ST7 ADDRESSING MODES (Cont’d) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait ...
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ST7 ADDRESSING MODES (Cont’d) 6.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST7263 6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL ...
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ST7263 INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2’s compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ELECTRICAL CHARACTERISTICS 7.1 ABSOLUTE MAXIMUM RATINGS Devices of the ST72 family contain circuitry to pro- tect the inputs against damage due to high static voltage or electric fields. Nevertheless recom- mended that normal precautions be observed in ...
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ST7263 7.2 THERMAL CHARACTERISTICS The average chip-junction temperature, T grees Celsius, may be calculated using the follow- ing equation Where: – the Ambient Temperature – ...
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OPERATING CONDITIONS General Operating Conditions ( +70°C unless otherwise specified) A Symbol Parameter 1) V Supply voltage DD f External clock frequency OSC Note 1: USB 1.1 specifies that the power supply must be between 4.00 ...
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ST7263 7.4 POWER CONSUMPTION ( +70°C unless otherwise specified) A GENERAL Symbol Parameter V Operating Supply Voltage DD V Analog Reference Voltage DDA CPU RUN mode (see Note 1) CPU WAIT mode (See Note ...
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I/O PORT CHARACTERISTICS ( +70°C unless otherwise specified) A STANDARD I/O PORT PINS Symbol Parameter Output Low Level Voltage Port A1, Port A2 (High Current open drain) Output Low Level Voltage Port A0 Port ...
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ST7263 7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS LOW VOLTAGE RESET Electrical Specifications Symbol Parameter Low Voltage Reset Threshold V IT+ V rising DD Low Voltage Reset Threshold V IT- V falling DD V Hysteresis (V hys IT+ 7.7 CONTROL TIMING ...
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COMMUNICATION INTERFACE CHARACTERISTICS The values given in the specifications of dedicated functions are generally not applicable for chips. Therefore, only the limits listed below are valid for the product 0... +70° otherwise specified 7.8.1 ...
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ST7263 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 44. USB: Data signal Rise and fall time Differential Data Lines VCRS USB: Low speed electrical characteristics Parameter Driver characteristics: Rise time Fall Time Rise/ Fall Time matching Output signal Crossover ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 7.8 Inter IC Control Interface 2 I C/DDC-Bus Timings Parameter Bus free time between a STOP and START con- dition Hold time START condition. After this period, the first clock pulse is ...
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ST7263 7.9 8-BIT ADC CHARACTERISTICS Digital Result ADCDR 255 V – V 254 DDA 1LSB = ---------------------------------------- - i deal 256 253 B(ideal ...
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ADC CHARACTERISTICS (Cont’d) R AIN V AIN Px.x/AINx C = input capacitance pin V = threshold voltage sampling switch C = sample/hold hold capacitance leakage = leakage current at the pin due to various junctions V ...
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ST7263 8 PACKAGE CHARACTERISTICS 8.1 PACKAGE MECHANICAL DATA Figure 45. 34-Pin Shrink Plastic Small Outline Package, 300-mil Width 0.10mm .004 seating plane Figure 46. 32-Pin Shrink Plastic Dual in Line Package, 400-mil Width See Lead Detail ...
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Figure 47. 32-Pin Shrink Ceramic Dual In-Line Package Dim. Min A A1 0.38 B 0.36 B1 0.64 C 0.20 D 29.41 29.97 30.53 1.158 1.180 1.202 9. Ø CDIP32SW N ST7263 mm ...
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... Standard (0 to +70° Ceramic DIP Subset index : 1 = fully featured; other number = downgraded versions Table 26. Ordering Information Program 1) Sales Type Memory (bytes) ST72E631K4D0 16K EPROM ST72631K4M1/xxx 16K ROM ST72T631K4M1 16K OTP ST72631K4B1/xxx 16K ROM ST72T631K4B1 16K OTP ST72632K2M1/xxx 8K ROM ST72T632K2M1 8K OTP ST72632K2B1/xxx 8K ROM ...
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... For marking, one line is possible with maximum 13 characters. Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. We have checked the ROM code verification file returned STMicroelectronics. It conforms exactly with the ROM code file orginally supplied. We therefore authorize STMicroelectronics to proceed with device manufacture ...
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ST7263 9.2 ST7 APPLICATION NOTES IDENTIFICATION PROGRAMMING AND TOOLS AN985 EXECUTING CODE IN ST7 RAM AN986 USING THE ST7 INDIRECT ADDRESSING MODE AN987 ST7 IN-CIRCUIT PROGRAMMING AN988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN989 STARTING WITH ST7 HIWARE C AN1039 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...