IS43DR16320B-25DBL

Manufacturer Part NumberIS43DR16320B-25DBL
ManufacturerISSI, Integrated Silicon Solution Inc
IS43DR16320B-25DBL datasheet
 

Specifications of IS43DR16320B-25DBL

Lead Free Status / Rohs StatusCompliant  
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IS43/46DR86400B, IS43/46DR16320B
required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a
REFRESH command.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When
in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including VREF) must be
maintained at valid levels upon entry/exit and during SELF REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon
entering self refresh and is automatically enabled upon exiting self refresh.
ODT (On-Die Termination)
The On-Die Termination feature allows the DDR2 SDRAM to easily implement an internal termination resistance (Rtt). For the x8
option, ODT can be configured for DQ[7:0], DQS, DQS#, DM, RDQS, and RDQS# signals. For the x16 option, ODT can be configured for
DQ[15:0], UDQS, LDQS, UDQS#, LDQS#, and UDM, and LDM signals. The ODT feature can be configured with the Extended Mode
Register Set (EMRS) command, and turned on or off using the ODT input signal. Before and after the EMRS is issued, the ODT input
must be received with respect to the timings of tAOFD, tMOD(max), tAOND; and the CKE input must be held HIGH throughout the
duration of tMOD(max).
The DDR2 SDRAM supports the ODT on and off functionality in Active, Standby, and Power Down modes, but not in Self Refresh
mode. ODT timing diagrams follow for Active/Standby mode and Power Down mode.
EMRS to ODT Update Delay
CK#
~
CK
EMRS
~
Command
~
ODT
tAOFD
Old Setting
ODT Timing for Active/Standby (Idle) Mode and Standard Active Power-Down Mode
CK#
~
CK
CKE
~
tIS
ODT
~
Internal Term.
~
Resistance
Notes:
1.
Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down Mode timings have to be applied.
2.
ODT turn-on time, tAON(Min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max, tAON(Max) is when the
ODT resistance is fully on. Both are measured from tAOND.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
NOP
NOP
tMOD(Max)
tMOD(Min)
0
1
2
tIS
VIH(AC)
tAXPD
NOP
NOP
tIS
ODT Ready
3
4
5
tIS
tANPD
VIL(AC)
tAOND
tAOFD
RTT
tAON(Min)
tAON(Max)
~
NOP
~
~
tAOND
Updated
6
7
tIS
tAOF(Min)
tAOF(Max)
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