IS43DR16320B-25DBL

Manufacturer Part NumberIS43DR16320B-25DBL
ManufacturerISSI, Integrated Silicon Solution Inc
IS43DR16320B-25DBL datasheet
 

Specifications of IS43DR16320B-25DBL

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IS43/46DR86400B, IS43/46DR16320B
DDR2 Extended Mode Register 3 (EMR[3]) Diagram
Address Field
BA1
Mode Register
1
Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3].
Truth Tables
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
Command Truth Table
Function
Previous
Cycle
(Extended) Mode Register
H
Refresh (REF)
H
Self Refresh Entry
H
Sel Refresh Exit
L
Single Bank Precharge
H
Precharge All Banks
H
Bank Activate
H
Write
H
Write with Auto Precharge
H
Read
H
Read with Auto Precharge
H
No Operation (NOP)
H
Device Deselect
H
Power Down Entry
H
Power Down Exit
L
Notes:
1.
All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
2.
Bank addresses BA0, BA1 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3.
Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" for details.
4.
The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements
5.
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6.
“X” means “H or L (but a defined logic level)”
7.
Self refresh exit is asynchronous.
8.
VREF must be maintained during Self Refresh operation.
9.
An refers to the MSBs of addresseses. An=A13 for x8, and An=A12 for x16.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
BA0
A13
A12
A11
A10
A9
1
0*
0*
0*
0*
0*
CKE
CS#
RAS#
CAS#
Current
Cycle
H
L
L
L
H
L
L
L
L
L
L
L
H
X
X
H
L
H
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
L
H
H
X
H
X
X
H
X
X
L
L
H
H
H
X
X
H
L
H
H
A8
A7
A6
A5
A4
A3
0*
0*
0*
0*
0*
0*
(9)
WE#
BA0-BA1
A10
An
-A11
Opcode
L
BA
H
X
X
X
H
X
X
X
X
X
X
X
H
BA
L
X
L
L
X
X
H
Row Address
H
BA
L
BA
X
L
L
BA
X
H
H
BA
X
L
H
BA
X
H
H
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
H
A2
A1
A0
0*
0*
0*
A9-A0
Notes
1, 2
X
1
X
1, 8
X
1, 7, 8
X
1, 2
X
1
1, 2
Column 1, 2, 3, 10
Column 1, 2, 3, 10
Column 1, 2, 3, 10
Column 1, 2, 3, 10
X
1
X
1
X
1,4
X
1, 4
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