ST72C334N2B6 STMicroelectronics, ST72C334N2B6 Datasheet
ST72C334N2B6
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ST72C334N2B6 Summary of contents
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MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES 8K or 16K Program memory (ROM or Single voltage FLASH) with read-out protection 256-bytes EEPROM Data memory In-Situ Programming (Remote ISP) Enhanced Reset System Low voltage supply ...
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PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 GENERAL DESCRIPTION . . . . . ...
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I/O Port Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Relative mode (Direct, Indirect ...
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PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334 8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection New ADC with a better accuracy and conversion time New configurable Clock, Reset and Supply system New power ...
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ST72334J/N, ST72314J/N, ST72124J 2 GENERAL DESCRIPTION 2.1 INTRODUCTION The ST72334J/N, ST72314J/N and ST72124J de- vices are members of the ST7 microcontroller fam- ily. They can be grouped as follows: – ST72334J/N devices are designed for mid-range applications with Data EEPROM, ...
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PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (HS) PE4 1 (HS) PE5 2 (HS) PE6 3 (HS) PE7 4 PB0 5 PB1 ...
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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Figure 3. 56-Pin SDIP Package Pinout PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 ...
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PIN DESCRIPTION (Cont’d) Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts PE1 / RDI PB0 PB1 PB2 PB3 PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN0 / PD0 AIN1 / ...
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ST72334J/N, ST72314J/N, ST72124J PIN DESCRIPTION (Cont’d) Legend / Abbreviations: Type input output supply Input level Dedicated analog input In/Output level CMOS 0. CMOS 0. Output ...
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Pin n Pin Name PF4/OCMP1_A I PF6 (HS)/ICAP1_A I PF7 (HS)/EXTCLK_A I DD_0 SS_0 ...
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ST72334J/N, ST72314J/N, ST72124J 2.3 REGISTER & MEMORY MAP As shown in the Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register locations, 384 ...
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REGISTER & MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PCDR 0005h Port C PCDDR 0006h PCOR 0007h 0008h PBDR 0009h Port B PBDDR 000Ah PBOR ...
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ST72334J/N, ST72314J/N, ST72124J Register Address Block Label 002Ah WATCHDOG WDGCR 002Bh CRSR 002Ch Data-EEPROM EECSR 002Dh 0030h 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh ...
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Register Address Block Label 0058h 006Fh 0070h ADCDR ADC 0071h ADCCSR 0072h to 007Fh Notes: 1) The bits corresponding to unavailable pins are forced hardware, this affects the reset status value. 2) External pin not available. 3) ...
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ST72334J/N, ST72314J/N, ST72124J 2.4 FLASH PROGRAM MEMORY 2.4.1 Introduction Flash devices have a single voltage non-volatile FLASH memory that may be programmed in-situ (or plugged in a programming tool byte-by- byte basis. 2.4.2 Main features Remote In-Situ Programming ...
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DATA EEPROM 2.6.1 Introduction The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 7. EEPROM Block ...
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 2.6.3 Memory Access The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 8 describes these different memory access ...
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DATA EEPROM (Cont’d) 2.6.4 Data EEPROM and Power Saving Modes Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler. The DATA EEPROM will immediately enter this mode if there ...
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ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d) 2.6.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h Bit 7:3 = Reserved, forced by hardware to 0. Bit Interrupt enable ...
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CENTRAL PROCESSING UNIT 3.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 3.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit ...
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ST72334J/N, ST72314J/N, ST72124J CENTRAL PROCESSING UNIT (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of ...
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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 SP2 The Stack Pointer is a 16-bit register which is al- ways pointing to the ...
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ST72334J/N, ST72314J/N, ST72124J 4 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72334J/N, ST72314J/N and ST72124J mi- crocontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing ...
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LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This means ...
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ST72334J/N, ST72314J/N, ST72124J 4.2 RESET SEQUENCE MANAGER (RSM) The reset sequence manager includes three RE- SET sources as shown in Figure 15: EXTERNAL RESET SOURCE pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the ...
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RESET SEQUENCE MANAGER (Cont’d) External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the input voltage. ...
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ST72334J/N, ST72314J/N, ST72124J RESET SEQUENCE MANAGER (Cont’d) Internal Low Voltage Detection RESET Two different RESET sequences caused by the in- ternal LVD circuitry can be distinguished: Power-On RESET Figure 17. LVD RESET Sequences DDnominal V LVDr V ...
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RESET SEQUENCE MANAGER (Cont’d) Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 18. Figure 18. Watchdog RESET Sequence DDnominal V LVDf RUN DELAY t DE LAYmin WATCHDOG UNDERFLOW ...
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ST72334J/N, ST72314J/N, ST72124J MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by 7 different sources coming from the multi-oscillator block: an external source 4 crystal or ceramic resonator oscillators 1 external RC oscillator 1 internal high frequency ...
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MULTI-OSCILLATOR (Cont’d) External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resis- tor and an external capacitor (see Figure 21). The selection of the external RC oscillator has ...
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ST72334J/N, ST72314J/N, ST72124J 4.3 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a clock filter ...
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SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION CLOCK RESET AND SUPPLY REGISTER (CRSR) Read/Write Reset Value: 000x 000x (00h) 7 LVD CSS Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF ...
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ST72334J/N, ST72314J/N, ST72124J 4.5 MAIN CLOCK CONTROLLER (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows to man- age the power saving modes such as the SLOW and ACTIVE-HALT modes. The whole ...
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MAIN CLOCK CONTROLLER (Cont’d) MISCELLANEOUS REGISTER 1 (MISCR1) See section 6.2 on page 47. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0001 (01h TB1 TB0 Bit 7:4 = Reserved, always read as 0. ...
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ST72334J/N, ST72314J/N, ST72124J 5 INTERRUPTS & POWER SAVING MODES 5.1 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt ...
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INTERRUPTS (Cont’d) Figure 26. Interrupt Processing Flowchart FROM RESET EXECU TE INSTRUCTION Table 6. Interrupt Mapping Source N Description Block RESET Reset TRAP Software Interrupt 0 Not used MCC Main Clock Controller Time Base Interrupt 1 CSS or Clock Security ...
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ST72334J/N, ST72314J/N, ST72124J 5.2 POWER SAVING MODES 5.2.1 Introduction To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7. After a RESET the normal ...
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POWER SAVING MODES (Cont’d) Standard HALT mode In this mode the main oscillator is turned off caus- ing all internal processing to be stopped, including the operation of the on-chip peripherals. All periph- erals are not clocked except the ones ...
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ST72334J/N, ST72314J/N, ST72124J POWER SAVING MODES (Cont’d) 5.2.3 WAIT Mode WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All ...
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POWER SAVING MODES (Cont’d) 5.2.4 SLOW Mode This mode has two targets: – To reduce power consumption by decreasing the internal clock in the device, – To adapt the internal clock frequency (f the available supply voltage. SLOW mode is ...
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ST72334J/N, ST72314J/N, ST72124J 6 ON-CHIP PERIPHERALS 6.1 I/O PORTS 6.1.1 Introduction The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for ...
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I/O PORTS (Cont’d) Figure 32. I/O Block Diagram ALTERNATE OUTPUT ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE (EIx) POLARITY SELECTION Table 8. Port Mode Options Configuration Mode Floating with/without ...
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) 6.1.3 I/O Port Implementation The I/O port register configurations are summa- rised as following. Standard Ports PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4 MODE DDR floating input pull-up input open drain output push-pull output ...
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I/O PORTS (Cont’d) 6.1.4 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bit 7:0 = ...
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ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d) Table 10. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 1) 0002h PAOR 0004h PCDR 0005h PCDDR ...
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MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 6.2.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the ISxx bits of ...
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ST72334J/N, ST72314J/N, ST72124J MISCELLANEOUS REGISTERS (Cont’d) 6.2.3 Miscellaneous Registers Description MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 CP1 Bit 7:6 = IS1[1:0] EI2 and EI3 sensitivity The interrupt sensitivity, defined using ...
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MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h BC1 BC0 - - Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 ...
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ST72334J/N, ST72314J/N, ST72124J 6.3 WATCHDOG TIMER (WDG) 6.3.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see ...
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ST72334J/N, ST72314J/N, ST72124J WATCHDOG TIMER (Cond’t) Table 13. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah 0 Reset Value 52/125 ...
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TIMER 6.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ( input ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 35. Timer Block Diagram f CPU 8 low 8 high 8-bit buffer EXEDG 16 16 BIT 1/2 FREE RUNNING 1/4 COUNTER 1/8 COUNTER ALTERNATE REGISTER 16 CC1 CC0 OVERFLOW EXTCLK DETECT CIRCUIT ICF1 ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MSB At t0 LSB is buffered Other instructions Returns the buffered Read LSB LSB value ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 36. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 37. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL ...
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TIMER (Cont’d) 6.4.3.3 Input Capture In this section, the index may The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 39. Input Capture Block Diagram ICAP1 pin EDGE DETECT EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 40. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi ...
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TIMER (Cont’d) 6.4.3.4 Output Compare In this section, the index may This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) Figure 41. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R Register OC2R Register Figure 42. Output Compare Timing Diagram, Internal Clock Divided by 2 INTERNAL CPU ...
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TIMER (Cont’d) 6.4.3.5 Forced Compare In this section i may represent The following bits of the CR1 register are used: FOLV2 FOLV1 OLVL2 When the FOLV i bit is set by software, the OLVL i bit ...
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ST72334J/N, ST72314J/N, ST72124J One Figure 44. Pulse Mode Timing Example .... FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 45. Pulse Width Modulation Mode Timing Example 34E2 FFFC FFFD FFFE COUNTER OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, ...
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TIMER (Cont’d) 6.4.3.7 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 6.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until ...
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TIMER (Cont’d) 6.4.6 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT ...
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TIMER (Cont’d) Table 15. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 Reset Value 0 Timer ...
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ST72334J/N, ST72314J/N, ST72124J 6.5 SERIAL PERIPHERAL INTERFACE (SPI) 6.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 47. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS ST72334J/N, ST72314J/N, ST72124J Internal Bus DR SPIF WCOL SPI STATE CONTROL SPIE SPE SPR2 MSTR MASTER CONTROL SERIAL ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.4 Functional Description Figure 46 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 49. Data Clock Timing Diagram CPOL = 1 CPOL = 0 MSBit Bit 6 MISO (from master) MSBit Bit 6 MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MSBit ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) 6.5.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) Table 17. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPISR SPIF 0023h Reset Value 0 82/125 6 ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 6.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 52. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE ILIE SCI INTERRUPT CONTROL TRANSMIT TER CLOCK f CPU /2 /16 84/125 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 52. It contains 6 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status register (SR) – A ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram EXTE NDED PRESCALER TRANSMITTE R RATE CONTROL EXTE NDED TRANS MITTER PRESCALE R REGISTER EXTE NDED RECEIVER PRESCALER REGISTER EXTE NDED PRESCALER RECEIVER ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows CPU (32 (32 PR ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 6.6.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR NF Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAK E - Bit Receive data bit 8. This bit is used to store the 9th bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 DR2 The Data register ...
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ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ERPR ...
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A/D CONVERTER (ADC) 6.7.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) 6.7.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If ...
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A/D CONVERTER (ADC) (Cont’d) 6.7.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 CH2 Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by ...
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ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d) Table 19. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Reset Value 0 98/125 ...
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INSTRUCTION SET 7.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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ST72334J/N, ST72314J/N, ST72124J ST7 ADDRESSING MODES (Cont’d) 7.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction Function NOP No operation TRAP ...
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ST7 ADDRESSING MODES (Cont’d) 7.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST72334J/N, ST72314J/N, ST72124J 7.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory tst ( ...
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ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Unsigned <= LD Load dst <= src MUL Multiply X NEG Negate (2’s compl) neg $10 NOP No Operation OR ...
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ELECTRICAL CHARACTERISTICS 8.1 ABSOLUTE MAXIMUM RATINGS This product contains devices for protecting the in- puts against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the specified ...
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ST72334J/N, ST72314J/N, ST72124J 8.2 RECOMMENDED OPERATING CONDITIONS GENERAL Symbol Parameter V Supply voltage DD Resonator oscillator frequency f OSC External clock source T Ambient temperature range A Figure 58. f Maximum Operating Frequency Versus V OSC FUNCTIONALI TY NOT GUARAN ...
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DC ELECTRICAL CHARACTERISTICS Recommended operating conditions with T Symbol Parameter Supply current in RUN mode Supply current in SLOW mode I DD Supply current in WAIT mode Supply current in SLOW WAIT mode Supply current in HALT mode 5) ...
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ST72334J/N, ST72314J/N, ST72124J 8.5 I/O PORT CHARACTERISTICS Recommended operating conditions o with T =-40 to +85 C and 4.5V< I/O PORT PINS Symbol Parameter 2) V Input low level voltage Input high level voltage IH ...
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SUPPLY, RESET AND CLOCK CHARACTERISTICS 8.6.1 Supply Manager Recommended operating conditions o with T =-40 to +85 C and voltage are referred LOW VOLTAG E DETECTOR (LVD) Symbol Parameter Reset release threshold V LVDr (V rise) ...
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ST72334J/N, ST72314J/N, ST72124J SUPPLY, RESET AND CLOCK CHARACTERISTICS (Cont’d) CRYSTAL AND CERAMIC RESONATOR OSCILLATORS Symbol Parameter 2) f Oscillator Frequency OSC Low speed Load Medium-low speed C Li Capacitance Medium-high speed High speed Low speed Supply Medium-low speed I DD ...
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MEMORY AND PERIPHERAL CHARACTERISTICS Recommended operating conditions o with T =-40 to +85 C and 3V< FLASH Program Memory Symbol Parameter t Typical programming time ISPPROG t Data retention RET N Write erase cycles RW Data-EEPROM ...
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ST72334J/N, ST72314J/N, ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) SPI Serial Peripheral Interface Ref. Symbol Parameter f SPI frequency SPI 1 t SPI clock period SPI 2 t Enable lead time Lead 3 t Enable lag time Lag 4 t Clock ...
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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Figure 60. SPI Master Timing Diagram CPHA=0, CPOL=1 SS (INPUT) SCK (OUTPUT) MISO D7-IN (INPUT MOSI D7-OUT (OUTPU T) 10 Figure 61. SPI Master Timing Diagram CPHA=1, CPOL=0 SS (INPUT) SCK (OUTPUT) 4 ...
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ST72334J/N, ST72314J/N, ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Measurement points are Figure 63. SPI Slave Timing Diagram CPHA=0, CPOL=0 SS (INPUT) 2 SCK (INPUT) 4 MISO HIGH-Z D7-OUT (OUTPU MOSI ...
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MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) SCI Serial Communication Interface Symbol Parameter Communication frequency (precision vs. standard ~0.16%) See “STANDARD I/O PORT PINS” description for more details. Note: 1) Unless otherwise specified, typical data are based ...
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ST72334J/N, ST72314J/N, ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) ADC Analog to Digital Converter (8-bit) Symbol Parameter f Analog control frequency ADC 4) |TUE| Total unadjusted error 4) OE Offset error 4) GE Gain Error 4) |DLE| Differential linearity error 4) ...
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GENERAL INFORMATION 9.1 PACKAGES 9.1.1 Package Mechanical Data Figure 67. 64-Pin Thin Quad Flat Package L1 Figure 68. 56-Pin Shrink Plastic Dual In-Line Package, 600-mil Width ST72334J/N, ST72314J/N, ST72124J Dim Min A A1 0.05 A2 1.35 1.40 1.45 0.053 ...
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ST72334J/N, ST72314J/N, ST72124J PACKAGES (Cont’d) Figure 69. 44-Pin Thin Quad Flat Package L1 Figure 70. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width 118/125 Dim Min A A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 ...
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PACKAGES (Cont’d) 9.1.2 User-supplied TQFP64 Adaptor / Socket To solder the TQFP64 device directly on the appli- cation board solder a socket for connecting the emulator probe, the application board should provide the footprint described in Figure 71. ...
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ST72334J/N, ST72314J/N, ST72124J PACKAGES (Cont’d) 9.1.3 User-supplied TQFP44 Adaptor / Socket To solder the TQFP44 device directly on the appli- cation board solder a socket for connecting the emulator probe, the application board should provide the footprint described ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM). FLASH devices are shipped to customers with a default content (FFh), while ROM factory ...
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... DEVICE PACKAGE RANGE XXX 122/125 The selected options are communicated to STMi- croelectronics using the correctly completed OP- TION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. Code name (defined by STMicroelectronics standard industrial - automotive -40 to +125 C ...
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... Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references Device ST72334J2 [ ] ST72334J4 [ ] ST72334N2 [ ] ST72334N4 ...
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ST72334J/N, ST72314J/N, ST72124J 10 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision New chapter to compare ST72334 versus ST72331 (section 2.1 on page 6) Correction of the address of ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...
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