M29W320DT90N6 Micron Technology Inc, M29W320DT90N6 Datasheet
M29W320DT90N6
Specifications of M29W320DT90N6
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M29W320DT90N6 Summary of contents
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... Program/Erase cycles per block Electronic Signature – Manufacturer Code: 0020h – Top Device Code M29W320DT: 22CAh – Bottom Device Code M29W320DB: 22CBh RoHS packages available Automotive Grade Parts Available February 2010 Boot Block), 3V Supply Flash memory TSOP48 ( 20mm TFBGA48 (ZE) Rev 12 M29W320DT M29W320DB FBGA 1/56 www ...
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Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Error Bit (DQ5 5.4 Erase Timer Bit (DQ3 5.5 Alternative Toggle Bit (DQ2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Appendix A Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix B Common Flash Interface (CFI Appendix C Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 C.1 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 C.2 In-System Technique Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3/56 ...
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List of tables Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic Diagram ...
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Summary description The M29W320D Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the ...
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Figure 1. Logic Diagram A0-A20 BYTE Table 1. Signal Names A0-A20 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block ...
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Figure 2. TSOP Connections 8/56 A15 1 48 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29W320DT M29W320DB /WP RB A18 A17 ...
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Figure 3. TFBGA48 Connections (Top view through package A17 A2 A6 A18 A20 ...
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Figure 4. Block Addresses (x8) M29W320DT Top Boot Block Addresses (x8) 3FFFFFh 16 KByte 3FC000h 3FBFFFh 8 KByte 3FA000h 3F9FFFh 8 KByte 3F8000h 3F7FFFh 32 KByte 3F0000h 3EFFFFh 64 KByte 3E0000h 01FFFFh 64 KByte 010000h 00FFFFh 64 KByte 000000h 1. ...
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Figure 5. Block Addresses (x16) M29W320DT Top Boot Block Addresses (x16) 1FFFFFh 8 KWord 1FE000h 1FDFFFh 4 KWord 1FD000h 1FCFFFh 4 KWord 1FC000h 1FBFFFh 16 KWord 1F8000h 1F7FFFh 32 KWord 1F0000h 00FFFFh 32 KWord 008000h 007FFFh 32 KWord 000000h 1. ...
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Signal descriptions See Figure 1: Logic connected to this device. 2.1 Address Inputs (A0-A20) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent ...
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Write Enable (W) The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. 2.8 V Write Protect (V PP/ The V /Write Protect pin provides two functions. The V PP use an external high voltage ...
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Ready/Busy Output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low Ready/Busy is high-impedance ...
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Bus operations There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See operations, for a summary. Typically glitches of less than 5ns on Chip Enable or ...
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Special bus operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. ...
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Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the ...
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... Read CFI Query command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area ...
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The memory uses the higher voltage on the V Protect pin, to accelerate the Unlock Bypass Program operation. Never raise V /Write Protect memory may be left in an indeterminate state. 4.6 Unlock Bypass ...
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Block Erase command The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list ...
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Erase Resume command The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended ...
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Table 4. Commands, 16-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X (3) Read/Reset 3 555 (4) Auto Select 3 555 (5) Program 4 555 (6) Unlock Bypass 3 ...
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Table 5. Commands, 8-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X (3) Read/Reset 3 AAA (4) Auto Select 3 AAA (5) Program 4 AAA (6) Unlock Bypass 3 ...
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Table 6. Program, Erase Times and Program, Erase Endurance Cycles Parameter Chip Erase Block Erase (64 KBytes) Erase Suspend Latency Time Program (Byte or Word) Accelerated Program (Byte or Word) Chip Program (Byte by Byte) Chip Program (Word by Word) ...
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Status Register Bus Read operations from any address always read the Status Register during Program and Erase operations also read during Erase Suspend when an address within a block being erased is accessed. The bits in the ...
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Error Bit (DQ5) The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data ...
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Table 7. Status Register Bits Operation Address Program Any Address Program During Erase Any Address Suspend Program Error Any Address Chip Erase Any Address Erasing Block Block Erase before timeout Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block ...
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Figure 7. Data Toggle Flowchart 28/56 START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C ...
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Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings ...
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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement ...
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Figure 1. AC Measurement Load Circuit V PP 0.1µ includes JIG capacitance Table 10. Device Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested DEVICE UNDER ...
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Table 11. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) CC1 I Supply Current (Standby) CC2 Supply Current (1) I CC3 (Program/Erase) V Input Low Voltage IL V Input High ...
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Figure 9. Read Mode AC Waveforms A0-A20/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH Table 12. Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC ...
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Figure 10. Write AC Waveforms, Write Enable Controlled A0-A20/ A–1 E tELWL G tGHWL W DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 13. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...
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Figure 11. Write AC Waveforms, Chip Enable Controlled A0-A20/ A–1 W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 14. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...
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Figure 12. Reset/Block Temporary Unprotect AC Waveforms tPLPX RP Table 15. Reset/Block Temporary Unprotect AC Characteristics Symbol Alt (1) t PHWL RP High to Write Enable Low, Chip Enable Low PHEL RH Output Enable ...
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Package mechanical Figure 14. TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Top View Package Outline DIE 1. Drawing not to scale. Table 16. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data millimeters ...
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Figure 15. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline FE BALL "A1" Drawing not to scale. Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data millimeters Symbol Typ ...
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Part numbering Table 18. Ordering Information Scheme Example: Device Type M29 Operating Voltage 2.7 to 3.6V CC Device Function 320D = 32 Mbit (x8/x16), Non-Uniform Parameter Blocks, Boot Block Array Matrix T = Top Boot ...
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Appendix A Block Addresses Table 19. Top Boot Block Addresses, M29W320DT Size # (KByte/KWor d) 66 16/8 65 8/4 64 8/4 63 32/16 62 64/32 61 64/32 60 64/32 59 64/32 58 64/32 57 64/32 56 64/32 55 64/32 54 ...
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Table 19. Top Boot Block Addresses, M29W320DT (continued) 35 64/32 34 64/32 33 64/32 32 64/32 31 64/32 30 64/32 29 64/32 28 64/32 27 64/32 26 64/32 25 64/32 24 64/32 23 64/32 22 64/32 21 64/32 20 64/32 ...
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Table 20. Bottom Boot Block Addresses, M29W320DB Size # (KByte/KWord) 66 64/32 65 64/32 64 64/32 63 64/32 62 64/32 61 64/32 60 64/32 59 64/32 58 64/32 57 64/32 56 64/32 55 64/32 54 64/32 53 64/32 52 64/32 ...
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Table 20. Bottom Boot Block Addresses, M29W320DB (continued) 32 64/32 31 64/32 30 64/32 29 64/32 28 64/32 27 64/32 26 64/32 25 64/32 24 64/32 23 64/32 22 64/32 21 64/32 20 64/32 19 64/32 18 64/32 17 64/32 ...
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... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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... Maximum timeout for chip erase = 2 Description n Device Size = 2 in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2 Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. ...
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Table 24. Device Geometry Definition (continued) Address Data x16 x8 31h 62h 0001h 32h 64h 0000h 33h 66h 0020h 34h 68h 0000h 35h 6Ah 0000h 36h 6Ch 0000h 37h 6Eh 0080h 38h 70h 0000h 39h 72h 003Eh 3Ah 74h 0000h ...
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Table 25. Primary Algorithm-Specific Extended Query Table (continued) Address Data x16 x8 4Dh 9Ah 00B5h 4Eh 9Ch 00C5h 4Fh 9Eh 000xh Table 26. Security Code Area Address Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, ...
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... Block Protection Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP ...
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Table 27. Programmer Technique Bus Operations, BYTE = V Operation E G Block Protect Chip Unprotect Block Protection Verify Block Unprotection Verify Address Inputs ...
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Figure 16. Programmer Equipment Block Protect Flowchart 50/56 START ADDRESS = BLOCK ADDRESS Wait 4µ Wait 100µ ...
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Figure 17. Programmer Equipment Chip Unprotect Flowchart NO ++n = 1000 FAIL START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = V IH (1) E, ...
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Figure 18. In-System Equipment Block Protect Flowchart 52/56 START WRITE 60h ADDRESS = BLOCK ADDRESS WRITE 60h ADDRESS = ...
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Figure 19. In-System Equipment Chip Unprotect Flowchart ++ 1000 ISSUE READ/RESET COMMAND FAIL START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH A0 ...
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Revision history Table 28. Document revision history Date Revision March-2001 08-Jun-2001 22-Jun-2001 27-Jul-2001 05-Oct-2001 07-Feb-2002 05-Apr-2002 19-Nov-2002 26-May-2003 16-Aug-2005 54/56 -01 First Issue (Brief Data) -02 Document expanded to full Product Preview Minor text corrections to Read/Reset and Read ...
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Table 28. Document revision history (continued) Date Revision Document title modified. TFBGA63 package removed. ECOPACK text added. RB signal updated in 13-Jun-2006 9 AC Unprotect AC In Program during Erase Suspend and Program Error. 26-Mar-2008 10 Applied Numonyx branding. Added ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...