ADV7393BCPZ Analog Devices Inc, ADV7393BCPZ Datasheet

IC DAC VIDEO HDTV 10BIT 40LFCSP

ADV7393BCPZ

Manufacturer Part Number
ADV7393BCPZ
Description
IC DAC VIDEO HDTV 10BIT 40LFCSP
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of ADV7393BCPZ

Design Resources
Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
Applications
Set-Top Boxes, Video Players, Displays
Voltage - Supply, Analog
2.6 V ~ 3.46 V
Voltage - Supply, Digital
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Input Format
Digital
Output Format
Analog
Supply Voltage Range
1.71V To 1.89V
Operating Temperature Range
-40°C To +85°C
Tv / Video Case Style
LFCSP
No. Of Pins
40
Msl
MSL 1 - Unlimited
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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FEATURES
3 high quality, 10-bit video DACs
Multiformat video input support
Multiformat video output support
Lead frame chip scale package (LFCSP) options
Wafer level chip scale package (WLCSP) option
Advanced power management
74.25 MHz 8-/10-/16-bit high definition input support
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
High definition (HD) programmable features
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098, and other intellectual property rights.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Component RGB (SD, ED, and HD)
30-ball, 5 × 6 WLCSP
(720p/1080i/1035i)
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
Compliant with SMPTE 274M (1080i), 296M (720p),
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (F
Luma delay
4× oversampling (297 MHz)
Internal test pattern generator
and 240M (1035i)
Color and black bar, hatch, flat field/frame
SC
) and phase
ADV7390/ADV7391/ADV7392/ADV7393
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Enhanced definition (ED) programmable features
Standard definition (SD) programmable features
Serial MPU interface with I
2.7 V or 3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
Qualification for automotive applications is in progress
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
16× oversampling (216 MHz)
Internal test pattern generator
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
10-Bit SD/HD Video Encoder
Color and black bar, hatch, flat field/frame
Color and black bar
composite/S-Video output
Low Power, Chip Scale,
©2006-2010 Analog Devices, Inc. All rights reserved.
2
C compatibility
www.analog.com

Related parts for ADV7393BCPZ

ADV7393BCPZ Summary of contents

Page 1

FEATURES 3 high quality, 10-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for maximum DAC output current Multiformat video input support 4:2:2 YCrCb ...

Page 2

ADV7390/ADV7391/ADV7392/ADV7393 TABLE OF CONTENTS Features .............................................................................................. 1 Revision History ............................................................................... 3 Applications ....................................................................................... 5 General Description ......................................................................... 5 Functional Block Diagrams ............................................................. 6 Specifications ..................................................................................... 7 Power Supply Specifications........................................................ 7 Input Clock Specifications .......................................................... 7 Analog Output Specifications ..................................................... 7 ...

Page 3

Copy Generation Management System ........................................ 74 SD CGMS ..................................................................................... 74 ED CGMS..................................................................................... 74 HD CGMS .................................................................................... 74 CGMS CRC Functionality ......................................................... 74 SD Wide Screen Signaling .............................................................. 77 SD Closed Captioning .................................................................... 78 Internal Test Pattern Generation ................................................... 79 SD ...

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ADV7390/ADV7391/ADV7392/ADV7393 Changes to Subaddress 0xBA Section .......................................... 56 Added Sleep Mode Section............................................................ 65 Changes to Pixel and Control Port Readback Section ............... 66 Changes to Reset Mechanisms Section ........................................ 66 Added SD Teletext Insertion Section ........................................... 66 Added Figure 87 ...

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APPLICATIONS Mobile handsets Digital still cameras Portable media and DVD players Portable game consoles Digital camcorders Set-top box (STB) Automotive infotainment (ADV7392 and ADV7393 only) GENERAL DESCRIPTION The ADV7390/ADV7391/ADV7392/ADV7393 are a family of high speed, digital-to-analog video encoders on single ...

Page 6

ADV7390/ADV7391/ADV7392/ADV7393 DGND (2) GND_IO VBI DATA SERVICE V DD_IO SDR/DDR 8-BIT SD SD/ED/HD INPUT OR 4:2:2 TO 4:4:4 8-BIT ED/HD DEINTERLEAVE POWER MANAGEMENT CONTROL RESET DGND (2) GND_IO VBI DATA SERVICE INSERTION V DD_IO SDR/DDR SD INPUT 8-BIT SD 4:2:2 ...

Page 7

SPECIFICATIONS POWER SUPPLY SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 3. Parameter SUPPLY VOLTAGES DD_IO POWER SUPPLY REJECTION RATIO INPUT CLOCK SPECIFICATIONS V = 1.71 ...

Page 8

ADV7390/ADV7391/ADV7392/ADV7393 DIGITAL INPUT/OUTPUT SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 6. Parameter Input High ...

Page 9

DIGITAL TIMING SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 9. Parameter VIDEO DATA AND ...

Page 10

ADV7390/ADV7391/ADV7392/ADV7393 DIGITAL TIMING SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 10. Parameter VIDEO DATA ...

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VIDEO PERFORMANCE SPECIFICATIONS Table 11. Parameter STATIC PERFORMANCE Resolution 1 Integral Nonlinearity (INL Differential Nonlinearity (DNL) STANDARD DEFINTION (SD) MODE Luminance Nonlinearity ...

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ADV7390/ADV7391/ADV7392/ADV7393 TIMING DIAGRAMS The following abbreviations are used in Figure 4 to Figure 11: • clock high time 9 • clock low time 10 • data setup time 11 • data hold ...

Page 13

CLKIN CONTROL HSYNC INPUTS VSYNC PIXEL PORT G0 PIXEL PORT PIXEL PORT R0 CONTROL OUTPUTS Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000 CLKIN CONTROL HSYNC INPUTS ...

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ADV7390/ADV7391/ADV7392/ADV7393 CLKIN* PIXEL PORT CONTROL OUTPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010 CLKIN CONTROL HSYNC INPUTS VSYNC PIXEL PORT t 11 CONTROL ...

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Y OUTPUT b HSYNC VSYNC PIXEL PORT PIXEL PORT PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A ...

Page 16

ADV7390/ADV7391/ADV7392/ADV7393 Y OUTPUT HSYNC VSYNC PIXEL PORT PIXEL PORT PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A ...

Page 17

HSYNC VSYNC PIXEL PORT Figure 16. SD Input Timing Diagram (Timing Mode SDA t 6 SCL t 2 Figure 17. MPU Port Timing Diagram (I ADV7390/ADV7391/ADV7392/ADV7393 PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK t t ...

Page 18

ADV7390/ADV7391/ADV7392/ADV7393 ABSOLUTE MAXIMUM RATINGS Table 13. 1 Parameter V to AGND DGND PGND GND_IO DD_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND ...

Page 19

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 DD_IO PIN INDICATOR ADV7390 ADV7391 DGND 6 TOP VIEW P5 7 (Not to Scale NOTES 1. THE EXPOSED PAD SHOULD BE ...

Page 20

ADV7390/ADV7391/ADV7392/ADV7393 Pin No. ADV7390/ ADV7392/ ADV7390 ADV7391 ADV7393 WLCSP 22, 21, 20 28, 27 ...

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TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response ED ...

Page 22

ADV7390/ADV7391/ADV7392/ADV7393 Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) Figure 27. HD 4× Oversampling, Y Filter Response Y PASS BAND IN ...

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Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 140 160 FREQUENCY (MHz) Figure 33. SD 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 ...

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ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. SD Luma QCIF Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 40. SD ...

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FREQUENCY (MHz) Figure 45. SD Chroma CIF Low-Pass Filter Response ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – Figure 46. SD Chroma QCIF ...

Page 26

ADV7390/ADV7391/ADV7392/ADV7393 MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the 2 ADV739x through a 2-wire serial (I C-compatible) bus. After power-up or reset, the MPU port is configured for I operation. To obtain information about communicating with ...

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SDA SCL S 1–7 8 START ADDR R/W ACK WRITE S SLAVE ADDR A(S) SUBADDR SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SUBADDR SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) ...

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ADV7390/ADV7391/ADV7392/ADV7393 REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV739x via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines the register accessed by ...

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SR7 to SR0 Register Bit Description 0x02 Mode Reserved Register 0 HD interlace external HSYNC and Test pattern black bar Manual CSC matrix adjust Sync on RGB RGB/YPrPb output select SD sync output enable ED/HD sync output enable 0x03 ED/HD ...

Page 30

ADV7390/ADV7391/ADV7392/ADV7393 Table 19. Register 0x0B to Register 0x17 SR7 to SR0 Register Bit Description 0x0B DAC 1, DAC 2, Positive gain to DAC output voltage DAC 3 output levels Negative gain to DAC output voltage 0x0D DAC power DAC 1 ...

Page 31

Table 20. Register 0x30 SR7 to SR0 Register Bit Description 0x30 ED/HD Mode ED/HD output standard Register 1 ED/HD input synchronization format ED/HD standard 1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC ...

Page 32

ADV7390/ADV7391/ADV7392/ADV7393 Table 21. Register 0x31 to Register 0x33 SR7 to SR0 Register Bit Description 0x31 ED/HD Mode ED/HD pixel data valid Register 2 HD oversample rate select ED/HD test pattern enable ED/HD test pattern hatch/field ED/HD vertical blanking interval (VBI) ...

Page 33

Table 22. Register 0x34 to Register 0x38 SR7 to SR0 Register Bit Description 0x34 ED/HD Mode ED/HD timing reset Register 5 ED/HD HSYNC control ED/HD VSYNC control Reserved ED Macrovision® enable Reserved ED/HD VSYNC input/field input ED/HD horizontal/vertical counter mode ...

Page 34

ADV7390/ADV7391/ADV7392/ADV7393 Table 23. Register 0x39 to Register 0x43 SR7 to SR0 Register Bit Description 0x39 ED/HD Mode Reserved Register 7 ED/HD EIA/CEA-861B synchronization compliance Reserved 0x40 ED/HD sharpness ED/HD sharpness filter gain filter gain Value A ED/HD sharpness filter gain ...

Page 35

Table 25. Register 0x58 to Register 0x5D SR7 to SR0 Register 0x58 ED/HD Adaptive Filter Gain 1 0x59 ED/HD Adaptive Filter Gain 2 0x5A ED/HD Adaptive Filter Gain 3 0x5B ED/HD Adaptive Filter Threshold A 0x5C ED/HD Adaptive Filter Threshold ...

Page 36

ADV7390/ADV7391/ADV7392/ADV7393 Table 26. Register 0x5E to Register 0x6E SR7 to SR0 Register Bit Description 0x5E ED/HD CGMS Type B ED/HD CGMS Type B Register 0 enable ED/HD CGMS Type B CRC enable ED/HD CGMS Type B header bits 0x5F ED/HD ...

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Table 27. Register 0x80 to Register 0x83 SR7 to SR0 Register Bit Description 0x80 SD Mode SD standard Register 1 SD luma filter SD chroma filter 0x82 SD Mode SD PrPb SSAF filter Register 2 SD DAC Output 1 Reserved ...

Page 38

ADV7390/ADV7391/ADV7392/ADV7393 Table 28. Register 0x84 to Register 0x87 SR7 to SR0 Register Bit Description 0x84 SD Mode Reserved Register 4 SD SFL/SCR/TR mode select SD active video length SD chroma SD burst SD color bars SD luma/chroma wwap 0x86 SD ...

Page 39

Table 29. Register 0x88 to Register 0x89 SR7 to SR0 Register Bit Description 0x88 SD Mode Register 7 Reserved SD noninterlaced mode SD double buffering SD input format SD digital noise reduction SD gamma correction enable SD gamma correction curve ...

Page 40

ADV7390/ADV7391/ADV7392/ADV7393 SR7 to SR0 Register Bit Description 0x8B SD Timing Register 1 SD HSYNC width Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit HSYNC to VSYNC delay SD HSYNC to VSYNC rising edge ...

Page 41

Table 31. Register 0x99 to Register 0xA5 SR7 to SR0 Register Bit Description 0x99 SD CGMS/WSS 0 SD CGMS data SD CGMS CRC SD CGMS on odd fields SD CGMS on even fields SD WSS 0x9A SD CGMS/WSS 1 SD ...

Page 42

ADV7390/ADV7391/ADV7392/ADV7393 SR7 to SR0 Register Bit Description 0xA4 SD DNR 1 DNR threshold Border area Block size 0xA5 SD DNR 2 DNR input select DNR mode DNR block offset Logic 0 or Logic 1. Table 32. Register ...

Page 43

SR7 to SR0 Register Bit Description 0xBB Field count Field count Reserved Encoder version code Logic 0 or Logic 1. See the HD Interlace External HSYNC and VSYNC Considerations section for information about the first encoder version. ...

Page 44

ADV7390/ADV7391/ADV7392/ADV7393 Table 34. Register 0xE0 to Register 0xF1 SR7 to 2 SR0 Register Bit Description 0xE0 Macrovision MV control bits 0xE1 Macrovision MV control bits 0xE2 Macrovision MV control bits 0xE3 Macrovision MV control bits 0xE4 Macrovision MV control bits ...

Page 45

ADV7390/ADV7391 INPUT CONFIGURATION The ADV7390/ADV7391 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7390/ADV7391 default to standard definition (SD) mode on power-up. Table 35 provides an overview of all possible ...

Page 46

ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION The ADV7392/ADV7393 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 default to standard definition (SD) mode on power-up. Table 36 provides an overview of all ...

Page 47

ENHANCED DEFINITION/HIGH DEFINITION Subaddress 0x01, Bits[6:4] = 001 or 010 YCrCb data can be input in a 4:2:2 format over an 8-/10-bit DDR bus or a 16-bit SDR bus. The clock signal must be provided on the ...

Page 48

ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION The ADV739x supports a number of different output configurations. Table 37 to Table 39 list all possible output configurations. Table 37. SD Output Configurations RGB/YPrPb Output Select 1 SD DAC Output 1 (Subaddress 0x02, Bit 5) (Subaddress ...

Page 49

DESIGN FEATURES OUTPUT OVERSAMPLING The ADV739x includes an on-chip phase-locked loop (PLL) that allows for oversampling of SD, ED, and HD video data. By default, the PLL is disabled. The PLL can be enabled using Subaddress 0x00, Bit 1 = ...

Page 50

ADV7390/ADV7391/ADV7392/ADV7393 HD INTERLACE EXTERNAL HSYNC AND VSYNC CONSIDERATIONS If the encoder revision code (Subaddress 0xBB, Bits[7:6 higher, the user should set Subaddress 0x02, Bit 1 to high. To ensure exactly correct timing in HD interlace modes when ...

Page 51

DISPL AY 307 NO F RESET APPLIED SC DISPLAY 307 F RESET APPLIED SC Figure 65. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01) COMPOSITE 1 VIDEO H/L TRANSITION COUNT START 128 RTC TIME SLOT 01 ...

Page 52

ADV7390/ADV7391/ADV7392/ADV7393 In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is ...

Page 53

ANALOG VIDEO EAV CODE INPUT PIXELS CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) 4 CLOCK PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE VIDEO LINE ...

Page 54

ADV7390/ADV7391/ADV7392/ADV7393 FILTERS Table 43 shows an overview of the programmable filters available on the ADV739x. Table 43. Selectable Filters Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD ...

Page 55

ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV739x includes a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by ...

Page 56

ADV7390/ADV7391/ADV7392/ADV7393 The SD CSC matrix scalar uses the following equations × × × × × ...

Page 57

SD LUMA AND COLOR SCALE CONTROL Subaddress 0x9C to Subaddress 0x9F When enabled, the SD luma and color scale control feature can be used to scale the SD Y, Cb, and Cr output levels. This feature can be enabled using ...

Page 58

ADV7390/ADV7391/ADV7392/ADV7393 To add a –7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 × Brightness Value ) = 0 × ( IRE Value × 2.075631 × (7 × 2.015631) = 0x(14.109417) ...

Page 59

The reset value of the control registers is 0x00; that is, nominal DAC current is output. Table example of how the output current of the DACs varies for a nominal 4.33 mA output current. Table 51. DAC ...

Page 60

ADV7390/ADV7391/ADV7392/ADV7393 The gamma curves in Figure 74 and Figure 75 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 300 250 SIGNAL OUTPUT 200 0.5 150 ...

Page 61

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5 1.4 1.3 1.2 1.1  INPUT SIGNAL 1.0 STEP 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka CH1 500mV REF A 500mV 4.00µs Block Figure 77. ...

Page 62

ADV7390/ADV7391/ADV7392/ADV7393 Figure 78. Input Signal to ED/HD Adaptive Filter Figure 79. Output Signal from ED/HD Adaptive Filter (Mode A) When the adaptive filter mode is changed to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 80 can ...

Page 63

Coring Gain Border—Subaddress 0xA3, Bits[3:0] These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values increments of 1/8. This factor is applied to the ...

Page 64

ADV7390/ADV7391/ADV7392/ADV7393 SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 The ADV739x is able to control fast rising and falling signals at the start and end of active video to minimize ringing. When the active video edge control feature is ...

Page 65

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the HSYNC and VSYNC pins (see signals on ...

Page 66

ADV7390/ADV7391/ADV7392/ADV7393 ED/HD VSYNC ED/HD Input ED/HD Sync Sync Format Control Output Enable (Subaddress (Subaddress (Subaddress 0x30, Bit 2) 0x34, Bit 2) 0x02, Bit all ED/HD standards where there is a VSYNC ...

Page 67

PIXEL AND CONTROL PORT READBACK Subaddress 0x13, Subaddress 0x14, Subaddress 0x16 The ADV739x supports the readback of most digital inputs via 2 the I C MPU port. This feature is useful for board-level connectivity testing with upstream devices. The pixel ...

Page 68

ADV7390/ADV7391/ADV7392/ADV7393 t SYNTTXOUT CVBS HSYNC 10.2µs TTX DATA TTX REQ TTX 10.2µs. SYNTTXOUT t = PIPELINE DELAY THROUGH ADV739x. PD TTX = TTX TO TTX (PROGRAMMABLE RANGE = 4 BITS [ PIXEL CLOCK ...

Page 69

PRINTED CIRCUIT BOARD LAYOUT AND DESIGN UNUSED PINS If the HSYNC and VSYNC pins are not used, they should be tied to V through a pull-up resistor (10 kΩ or 4.7 kΩ). Any DD_IO other unused digital inputs should be ...

Page 70

ADV7390/ADV7391/ADV7392/ADV7393 CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 –40 –50 GROUP DELAY (Seconds) –60 –70 –80 1M 10M 100M FREQUENCY (Hz) Figure 93. Output Filter Plot for SD, 16× Oversampling CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 GROUP DELAY (Seconds) ...

Page 71

Power Supply Decoupling It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The and both V pins should be individually decoupled to DD_IO DD ground. The decoupling capacitors ...

Page 72

ADV7390/ADV7391/ADV7392/ADV7393 TYPICAL APPLICATIONS CIRCUITS FERRITE BEAD V DD_IO 33µF 10µF GND_IO GND_IO FERRITE BEAD PV DD 33µF 10µF PGND PGND FERRITE BEAD V AA 33µF 10µF AGND AGND FERRITE BEAD V DD 33µF 10µF DGND DGND ...

Page 73

FERRITE BEAD V DD_IO 33µF 10µF GND_IO GND_IO FERRITE BEAD PV DD 33µF 10µF PGND PGND FERRITE BEAD V AA 33µF 10µF AGND AGND FERRITE BEAD V DD 33µF 10µF DGND DGND PIXEL PORT INPUTS P4 ...

Page 74

ADV7390/ADV7391/ADV7392/ADV7393 COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV739x supports a copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd ...

Page 75

IRE +70 IRE 0 IRE –40 IRE 11.2µs +700mV 70% ± 10% 0mV –300mV 5.8µs ± 0.15µs 6T PEAK WHITE 500mV ± 25mV SYNC LEVEL 5.5µs ± 0.125µs +700mV REF 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns ...

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ADV7390/ADV7391/ADV7392/ADV7393 +700mV 70% ± 10% 0mV –300mV 4T 4.15µs ± 60ns +700mV 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. +700mV 70% ±10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A ...

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SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV739x supports wide screen signaling (WSS) con- forming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the ...

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ADV7390/ADV7391/ADV7392/ADV7393 SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV739x supports closed captioning conforming to the standard television synchronizing waveform for color trans- mission. When enabled, closed captioning is transmitted during the blanked active line time of Line 21 ...

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INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV739x is able to internally generate SD color bar and black bar test patterns. For this function MHz clock signal must be applied to the CLKIN pin. The register settings ...

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ADV7390/ADV7391/ADV7392/ADV7393 SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the ...

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DISPLAY 622 623 624 625 H F EVEN FIELD DISPLAY 309 310 311 312 H ODD FIELD F ANALOG VIDEO H F Mode 1—Slave Option (Subaddress 0x8A = this mode, the ...

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ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY 622 623 624 625 HSYNC FIELD EVEN FIELD DISPLAY 309 310 311 312 HSYNC FIELD ODD FIELD Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV739x can generate ...

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DISPLAY 522 523 524 525 HSYNC VSYNC DISPLAY 260 261 262 263 HSYNC VSYNC DISPLAY 622 623 624 HSYNC VSYNC EVEN FIELD DISPLAY 309 310 311 HSYNC VSYNC ODD FIELD Mode 2—Master Option (Subaddress 0x8A = ...

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ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC PIXEL DATA Figure 117. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = this ...

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HD TIMING FIELD 1 1124 1125 VSYNC HSYNC FIELD 2 561 562 VSYNC HSYNC ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 120. 1080i HSYNC and ...

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ADV7390/ADV7391/ADV7392/ADV7393 VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 121. Y Levels—NTSC 700mV Figure 122. Pr Levels—NTSC 700mV Figure 123. Pb Levels—NTSC 700mV 300mV Figure 124. Y Levels—PAL 700mV Figure 125. Pr Levels—PAL ...

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ED/HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 127. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 ...

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ADV7390/ADV7391/ADV7392/ADV7393 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 131. SD/ED RGB Output Levels—RGB Sync Disabled R 700mV/525mV 300mV 0mV G 700mV/525mV 300mV 0mV B 700mV/525mV 300mV 0mV Figure 132. ...

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SD OUTPUT PLOTS VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72μs µ FRAMES ...

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ADV7390/ADV7391/ADV7392/ADV7393 VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 ...

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ACTIVE VIDEO 622 623 624 625 Figure 144. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 1 2 747 748 749 750 VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 VERTICAL BLANKING INTERVAL FIELD 2 561 562 ...

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ADV7390/ADV7391/ADV7392/ADV7393 CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 64 lists ...

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Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma ...

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ADV7390/ADV7391/ADV7392/ADV7393 Table 72. 10-Bit 525i YCrCb In, CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma ...

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Table 78. 16-Bit 525i RGB In, CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter ...

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ADV7390/ADV7391/ADV7392/ADV7393 Table 84. 8-Bit 625i YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz chroma ...

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Table 91. 10-Bit 625i YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x11 PAL ...

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ADV7390/ADV7391/ADV7392/ADV7393 Table 97. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV), CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x10 WLCSP required. 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF ...

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ENHANCED DEFINITION Table 99. ED Configuration Scripts Input Format Input Data Width 525p 8-bit DDR 525p 8-bit DDR 525p 10-bit DDR 525p 10-bit DDR 525p 16-bit SDR 525p 16-bit SDR 525p 16-bit SDR 525p 16-bit SDR 625p 8-bit DDR 625p ...

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ADV7390/ADV7391/ADV7392/ADV7393 Table 106. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 ...

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Table 114. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB ...

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ADV7390/ADV7391/ADV7392/ADV7393 Table 117. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x30 0x2C 720p at 60 Hz/59.94 Hz. EAV/SAV syn- chronization. ...

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Table 127. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB ...

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ADV7390/ADV7391/ADV7392/ADV7393 ADV739X EVALUATION BOARD To accommodate evaluation of the ADV7390/ADV7391/ ADV7392/ADV7393, Analog Devices provides a two-board solution. The ADV739x evaluation platform front-end board contains an Analog Devices decoder (ADV7403) and an FPGA. The back-end board (where the actual ADV739x is ...

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OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ADV7390/ADV7391/ADV7392/ADV7393 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0.50 0.40 17 0.30 ...

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... ADV7392BCPZ-3REEL −40°C to +85°C ADV7392WBCPZ −40°C to +85°C ADV7392WBCPZ-REEL −40°C to +85°C ADV7393BCPZ −40°C to +85°C ADV7393BCPZ-REEL −40°C to +85°C ADV7393WBCPZ −40°C to +85°C ADV7393WBCPZ-REEL −40°C to +85°C EVAL-ADV739xFEZ EVAL-ADV7390EBZ EVAL-ADV7390-AEBZ ...

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NOTES ADV7390/ADV7391/ADV7392/ADV7393 Rev Page 107 of 108 ...

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ADV7390/ADV7391/ADV7392/ADV7393 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2006-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06234-0-7/10(B) Rev ...

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