ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet

IC VIDEO DECODER NTSC 64-LFCSP

ADV7181BCP

Manufacturer Part Number
ADV7181BCP
Description
IC VIDEO DECODER NTSC 64-LFCSP
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheets

Specifications of ADV7181BCP

Applications
Recorders, Set-Top Boxes
Voltage - Supply, Analog
3.15 V ~ 3.45 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Adc/dac Resolution
9b
Screening Level
Industrial
Package Type
LFCSP EP
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
Lead Free Status / RoHS Status
Compliant, Contains lead / RoHS non-compliant
FEATURES
Multiformat video decoder supports NTSC-(M, J, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™),
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision
Chroma transient improvement (CTI)
Digital noise reduction (DNR)
Multiple programmable analog input formats
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit)
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
Differential phase: 0.6° typ
GENERAL DESCRIPTION
The ADV7181B integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-bit/8-bit
CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The six analog input channels accept standard composite,
S-Video, and YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively,
these can be bypassed for manual settings.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
unstable video sources such as VCRs and tuners
Composite video (CVBS)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
signal processing, and enhanced FIFO management
give mini-TBC functionality
®
copy protection detection
Multiformat SDTV Video Decoder
Programmable video controls
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for
VBI decode support for
Power-down mode
2-wire serial MPU interface (I
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade: –40°C to +85°C
64-lead LQFP Pb-free package and 64-lead LFCSP package
APPLICATIONS
DVD recorders
PC video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receivers
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181B modes
are set up over a 2-wire, serial, bidirectional port (I
The ADV7181B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181B is available in two packages, a small 64-lead
LQFP Pb-free package and a 64-lead LFCSP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Peak white/hue/brightness/saturation/contrast
close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
close captioning, WSS, CGMS, EDTV, and
Gemstar® 1×/2×
© 2005 Analog Devices, Inc. All rights reserved.
2
C®-compatible)
ADV7181B
www.analog.com
2
C-compatible).

Related parts for ADV7181BCP

ADV7181BCP Summary of contents

Page 1

FEATURES Multiformat video decoder supports NTSC-(M, J, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, 9-bit ADCs Clocked from a single 27 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™), signal processing, and enhanced FIFO management give mini-TBC ...

Page 2

ADV7181B TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Functional Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ ...

Page 3

Typical Circuit Connection ...........................................................97 Outline Dimensions........................................................................99 REVISION HISTORY 9/05—Rev Rev. B Changes to Table 1 ............................................................................6 Changes to Table 2 ............................................................................7 Changes to Table 3 and Table 4 .......................................................8 Changes to Table 5 ............................................................................9 Changes to Figure 5.........................................................................13 ...

Page 4

ADV7181B INTRODUCTION The ADV7181B is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced ...

Page 5

FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER Figure 1. Rev Page 5 of 100 ADV7181B ...

Page 6

ADV7181B SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD VDD otherwise noted. Table Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input ...

Page 7

VIDEO SPECIFICATIONS Guaranteed by characterization 3. 3. VDD operating temperature range, unless otherwise noted. Table Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End ...

Page 8

ADV7181B TIMING SPECIFICATIONS Guaranteed by characterization 3. 3. VDD operating temperature range, unless otherwise noted. Table Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability PORT SCLK Frequency ...

Page 9

THERMAL SPECIFICATIONS Table Parameter THERMAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance 1 Temperature range –40°C to +85°C MIN MAX 2 The min/max ...

Page 10

ADV7181B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to GND 4 V VDD A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO D to ...

Page 11

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTRQ HS DGND DVDDIO P11 P10 P9 P8 SFL DGND 10 DVDDIO CONNECT ...

Page 12

ADV7181B Table 7. Pin Function Descriptions Pin No. Mnemonic Type 3, 10, 24, 34, 57 DGND G 32, 37, 43, 45 AGND DVDDIO P 23, 58 DVDD P 40 AVDD P 31 PVDD P 35, 36, 46 ...

Page 13

ANALOG FRONT END The two key steps to configure the ADV7181B to correctly decode the input video are: • The analog input muxing section must be configured to correctly route the video from the analog input pins to the correct ...

Page 14

ADV7181B Table 8. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1) ADC0_sw[3:0] ADC0 Connected to 0000 No connection 0001 AIN2 0010 No connection 0011 No connection 0100 AIN4 0101 AIN6 0110 No connection 0111 No connection 1000 No connection ...

Page 15

GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. POWER-SAVE MODES Power-Down The digital core of the ADV7181B can be shut down by using a pin ( PWRDN ) and a bit (PWRDN); see below. ...

Page 16

ADV7181B GLOBAL PIN CONTROL Three-State Output Drivers TOD, Address 0x03[6] This bit allows the user to three-state the output drivers of the ADV7181B. Upon setting the TOD bit, the P15 to P0, HS, VS, FIELD, and SFL pins are three-stated. ...

Page 17

Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04[1] The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7181B core to an encoder in a decoder-encoder back-to-back arrangement. When EN_SFL_PIN is 0 (default), the ...

Page 18

ADV7181B GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7181B. The other three registers contain status bits from the ADV7181B. IDENTIFICATION IDENT[7:0] Address ...

Page 19

STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION DIGITIZED CVBS LUMA DIGITIZED Y (YC) DIGITAL FINE CLAMP DIGITIZED CVBS CHROMA DIGITIZED C (YC) DIGITAL CHROMA FINE DEMOD CLAMP RECOVERY A block diagram of the ADV7181B’s standard definition processor (SDP) ...

Page 20

ADV7181B SYNC PROCESSING The ADV7181B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches. The ...

Page 21

AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07 [6] Setting AD_SECAM_EN to 0 (default) disables the autodetection of SECAM. Setting AD_SECAM_EN to 1 enables the detection. AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07 [5] Setting AD_N443_EN to 0 disables the ...

Page 22

ADV7181B SRLS Select Raw Lock Signal, Address 0x51[6] Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status 1 register). • The time_win signal is based on a line-to-line ...

Page 23

SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4[7:0] This register allows the user to control the gain of the Cr channel only, which in turn adjusts the saturation of the picture. Table 23. SD_SAT_Cr Function SD_SAT_Cr[7:0] Description 0x80 (default) Gain on ...

Page 24

ADV7181B DEF_VAL_EN Default Value Enable, Address 0x0C[0] This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a ...

Page 25

The following sections describe the I C signals that can be used to influence the behavior of the clamping block. Previous revisions of the ADV7181B had controls (FACL/FICL, fast and fine clamp length) to allow configuration of the length ...

Page 26

ADV7181B Y-Shaping Filter For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. YC separation must aim for the best possible crosstalk reduction while still retaining as ...

Page 27

BAD AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB Table 29. YSFM Function YSFM[4:0] Description 0'0000 Automatic selection including a wide notch response (PAL/NTSC/SECAM) 0'0001 Automatic selection including a narrow notch (default) response (PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 ...

Page 28

ADV7181B The filter plots in Figure 11 show the S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter settings. Figure 13 shows the PAL notch filter responses. The NTSC-compatible notches are shown in Figure 14. COMBINED Y ANTIALIAS, S-VHS LOW-PASS ...

Page 29

CSFM[2:0] C Shaping Filter Mode, Address 0x17[7] The C shaping filter mode bits allow the user to select from a range of low-pass filters, SH1 to SH5 and wideband mode, for the chrominance signal. The autoselection options automati- cally select ...

Page 30

ADV7181B Table 32. AGC Modes Input Video Type Luma Gain Any Manual gain luma CVBS Dependent on horizontal sync depth Peak white Y/C Dependent on horizontal sync depth Peak white YPrPb Dependent on horizontal sync depth Luma Gain LAGC[2:0] Luma ...

Page 31

For example, program the ADV7181B into manual fixed gain mode with a desired gain of 0.89. 1. Use Equation 1 to convert the gain: 0.89 × 2048 = 1822.72 2. Truncate to integer value: 1822.72 = 1822 3. Convert to ...

Page 32

ADV7181B CG[11:0] Chroma Gain, Address 0x2D[3:0]; Address 0x2E[7:0]; CMG[11:0] Chroma Manual Gain, Address 0x2D[3:0]; Address 0x2E[7:0] Chroma gain[11: dual-function register. If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] ...

Page 33

The chroma transient improvement block examines the input video data. It detects transitions of chroma, and can be programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth. The CTI block, however, operates only on ...

Page 34

ADV7181B NSFSEL[1:0] Split Filter Selection NTSC, Address 0x19[3:2] The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A narrow split filter selection gives better performance on diagonal lines, but leaves more dot crawl ...

Page 35

CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6] Table 48. CTAPSP Function CTAPSP[1:0] Description 00 Do not use 01 PAL chroma comb adapts 5 lines (3 taps lines (2 taps); cancels cross luma only 10 PAL chroma comb adapts ...

Page 36

ADV7181B AV CODE INSERTION AND CONTROLS 2 This section describes the I C-based controls that affect: • Insertion of AV codes into the data stream. • Data blanking during the vertical blank interval (VBI). • The range of data values ...

Page 37

BL_C_VBI Blank Chroma During VBI, Address 0x04[2] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines are blanked. This is done so any data that may arrive during VBI is not decoded as color and output through ...

Page 38

ADV7181B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: • Beginning of HS signal via HSB[10:0] • End of HS signal via HSE[10:0] • Polarity of HS ...

Page 39

VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as the generation of embedded AV codes: • ADV encoder-compatible signals via NEWAVMODE • PVS, PF • ...

Page 40

ADV7181B PF Polarity FIELD, Address 0x37[3] The polarity of the FIELD pin can be inverted using the PF bit. The FIELD pin can be inverted using the PF bit. 525 1 2 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F ...

Page 41

Table 55. Recommended User Settings for NTSC (See Figure 21) Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE5 0xE6 0xE7 NVBEGDELO NTSC Vsync Begin Delay on Odd Field, Address 0xE5[7] When NVBEGDELO is 0 (default), there is no delay. ...

Page 42

ADV7181B NVENDDELO NTSC Vsync End Delay on Odd Field, Address 0xE6[7] When NVENDDELO is 0 (default), there is no delay. Setting NVENDDELO to 1 delays Vsync from going low on an odd field by a line relative to NVEND. NVENDDELE ...

Page 43

Table 56. Recommended User Settings for PAL (see Figure 26) Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE8 0xE9 0xEA NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7[5] Setting NFTOGSIGN to 0 delays the field transition. Set for user manual ...

Page 44

ADV7181B 622 623 624 625 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 310 311 312 313 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 Figure 25. PAL Default (BT.656). The Polarity of H, ...

Page 45

PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES PVBEGDELO ADDITIONAL DELAY BY 1 LINE VSBHO ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 27. PAL Vsync Begin ...

Page 46

ADV7181B PVEND[4:0] PAL Vsync End, Address 0xE9[4:0] The default value of PVEND is 10100, indicating the PAL Vsync end position. For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS ...

Page 47

The closed captioning data (CCAP) is available in the I registers, and is also inserted into the output video data stream during horizontal blanking. The Gemstar-compatible data is not available in the I registers, and is inserted into the data ...

Page 48

ADV7181B Table 57. WSS Access Information Signal Name Register Location WSS1[7:0] WSS 1[7:0] WSS2[5:0] WSS 2[5:0] 0 Table 58. EDTV Access Information Signal Name Register Location EDTV1[7:0] EDTV 1[7:0] EDTV2[7:0] EDTV 2[7:0] EDTV3[7:0] EDTV 3[7:0] CGMS Data Registers CGMS1[7:0], Address ...

Page 49

Table 59. CGMS Access Information Signal Name Register Location CGMS1[7:0] CGMS 1[7:0] CGMS2[7:0] CGMS 2[7:0] CGMS3[3:0] CGMS 3[3:0] 10.5 50 IRE 40 IRE REFERENCE COLOR BURST FREQUENCY = F AMPLITUDE = 40 IRE 10.003μs Table 60. CCAP Access Information Signal ...

Page 50

ADV7181B LB_LCT[7:0] Letterbox Line Count Top, Address 0x9B[7:0]; LB_LCM[7:0] Letterbox Line Count Mid, Address 0x9C[7:0]; LB_LCB[7:0] Letterbox Line Count Bottom, Address 0x9D[7:0] Table 61. LB_LCx Access Information Signal Name Address Register Default Value LB_LCT[7:0] 0x9B Readback only LB_LCM[7:0] 0x9C Readback ...

Page 51

DATA IDENTIFICATION PREAMBLE FOR ANCILLARY DATA Table 63. Generic Data Output Packet Byte D[9] D[ ...

Page 52

ADV7181B • CS[8:2]. The checksum is provided to determine the integrity of the ancillary data packet calculated by summing up D[8:2] of DID, SDID, the data count byte, and all UDWs, and ignoring any overflow during the summation. ...

Page 53

Table 67. Gemstar 1× Data, Half-Byte Mode Byte D[9] D[ ...

Page 54

ADV7181B NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0; the full-byte mode is enabled by CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section. The data packet formats are shown ...

Page 55

Table 72. PAL CCAP Data, Full-Byte Mode Byte D[9] D[ ...

Page 56

ADV7181B Table 73. NTSC Line Enable Bits and Corresponding Line Numbering Line Number Line[3:0] (ITU-R BT.470) Enable Bit 0 10 GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[6] 7 ...

Page 57

IF Compensation Filter IF FILTSEL[2:0] IF Filter Select Address 0xF8[2:0] The IF FILTSEL[2:0] register allows the user to compensate for SAW filter characteristics on a composite input as would be observed on tuner outputs. Figure 35 and Figure 36 show ...

Page 58

ADV7181B INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[1:0] Table 76. INTRQ_OP_SEL INTRQ_OP_SEL[1:0] Description 00 Open drain (default) 01 Drive low when active 10 Drive high when active 11 Reserved Multiple Interrupt Events If Interrupt Event 1 occurs and then ...

Page 59

PIXEL PORT CONFIGURATION The ADV7181B has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. Table 78 and Table 79 summarize the various functions that the ADV7181B pins can have ...

Page 60

ADV7181B MPU PORT DESCRIPTION 2 The ADV7181B supports a 2-wire (I C-compatible) serial inter- face. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7181B and the system I master controller. Each slave device is recognized ...

Page 61

REGISTER ACCESSES The MPU can write to or read from all of the ADV7181B’s registers, except the subaddress register, which is write only. The subaddress register determines which register the next read or write operation accesses. All communications with the ...

Page 62

ADV7181B REGISTER MAPS Table 81. Common and Normal (Page 1) Register Map Details Register Name Input Control Video Selection Reserved Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default ...

Page 63

Register Name Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free-Run Line Length ...

Page 64

ADV7181B Register Name Drive Strength Reserved IF Comp Control VS Mode Control Table 82. Common and Normal (Page 1) Register Map Bit Names Register Name Bit 7 Bit 6 Input Control VID_SEL.3 VID_SEL.2 Video ENHSPLL Selection Reserved Output VBI_EN TOD ...

Page 65

Register Name Bit 7 Bit 6 Luma Gain LMG.7 LMG.6 Control 2 Vsync Field Control 1 Vsync Field VSBHO VSBHE Control 2 Vsync Field VSEHO VSEHE Control 3 Hsync HSB.10 Position Control 1 Hsync HSB.7 HSB.6 Position Control 2 Hsync ...

Page 66

ADV7181B Register Name Bit 7 Bit 6 Letterbox Control 1 Letterbox LB_SL.3 LB_SL.2 Control 2 Reserved Reserved Reserved SD Offset Cb SD_OFF_CB.7 SD_OFF_CB.6 SD Offset Cr SD_OFF_CR.7 SD_OFF_CR.6 SD Saturation SD_SAT_CB.7 SD_SAT_CB Saturation SD_SAT_CR.7 SD_SAT_CR.6 Cr NTSC V ...

Page 67

I C REGISTER MAP DETAILS The following registers are located in Register Access Page 2. Table 83. Interrupt Register Map Bit Names Subaddress Register Reset Name Value rw Dec Interrupt 0001 x000 rw 64 Config 0 Reserved 65 Interrupt ...

Page 68

ADV7181B Table 84. Interrupt Register Map Details Subaddress Register Bit Description 0x40 Interrupt INTRQ_OP_SEL[1:0]. Config 1 Interrupt Drive Level Select. Register Access MPU_STIM_INTRQ[1:0]. Page 2 Manual Interrupt Set Mode. Reserved. MV_INTRQ_SEL[1:0]. Macrovision Interrupt Select. INTRQ_DUR_SEL[1:0]. Interrupt Duration Select. 0x41 Reserved ...

Page 69

Subaddress Register Bit Description 0x44 Interrupt SD_LOCK_MSKB. Mask 1 SD_UNLOCK_MSKB. Read/Write Register Reserved. Reserved. Register Reserved. Access Page 2 SD_FR_CHNG_MSKB. MV_PS_CS_MSKB. Reserved. 0x45 Reserved 0x46 Interrupt CCAPD_Q. Status 2 Read Only Register GEMD_Q. Register Access Page 2 CGMS_CHNGD_Q. WSS_CHNGD_Q. Reserved. ...

Page 70

ADV7181B Subaddress Register Bit Description 0x48 Interrupt CCAPD_MSKB. Mask 2 GEMD_MSKB. Read/ Write CGMS_CHNGD_MSKB. Register WSS_CHNGD_MSKB. Access Page 2 Reserved. Reserved. Reserved. MPU_STIM_INTRQ_MSKB. 0x49 Raw SD_OP_50Hz. Status 3 SD 60/50Hz frame rate at output. SD_V_LOCK. Read Only Register SD_H_LOCK. Register ...

Page 71

Subaddress Register Bit Description 0x4B Interrupt SD_OP_CHNG_CLR. Clear 3 SD_V_LOCK_CHNG_CLR. Write Only Register SD_H_LOCK_CHNG_CLR. Register SD_AD_CHNG_CLR. Access Page 2 SCM_LOCK_CHNG_CLR. PAL_SW_LK_CHNG_CLR. Reserved. Reserved. 0x4C Interrupt SD_OP_CHNG_MSKB. Mask 2 SD_V_LOCK_CHNG_MSKB. Read / Write Register SD_H_LOCK_CHNG_MSKB. Register Access SD_AD_CHNG_MSKB. Page 2 SCM_LOCK_CHNG_MSKB. ...

Page 72

ADV7181B Table 85. Common and Normal (Page 1) Register Map Details Subaddress Register Bit Description 0x00 Input INSEL[3:0]. The INSEL bits allow the Control user to select an input channel as well as the input format. VID_SEL[3:0]. The VID_SEL bits ...

Page 73

Subaddress Register Bit Description 0x03 Output SD_DUP_AV. Duplicates the AV Control codes from the Luma into the chroma path. Reserved. OF_SEL[3:0]. Allows the user to choose from a set of output formats. TOD. Three-state output drivers. This bit allows the ...

Page 74

ADV7181B Subaddress Register Bit Description 0x07 Autodetect E AD_PAL_EN. PAL B/G/I/H autodetect nable enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL60 autodetect enable. AD_N443_EN. NTSC443 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. ...

Page 75

Subaddress Register Bit Description 0x0F Power Reserved. Management PDBP. Power-down bit priority selects between PWRDN bit and PIN. Reserved. PWRDN. Power-down places the decoder in a full power-down mode. Reserved. RES. Chip reset loads all I default values. 0x10 Status ...

Page 76

ADV7181B Subaddress Register Bit Description Analog 0x14 Reserved. Clamp CCLEN. Current clamp enable allows Control the user to switch off the current sources in the analog front. Reserved. 0x15 Digital Reserved. Clamp DCT[1:0]. Digital clamp timing Control 1 determines the ...

Page 77

Subaddress Register Bit Description 0x18 Shaping WYSFM[4:0]. Wideband Y shaping Filter filter mode allows the user to select Control 2 which Y shaping filter is used for the Y component of Y/C, YPbPr, B/W input signals also used ...

Page 78

ADV7181B Subaddress Register Bit Description 0x27 Pixel Delay LTA[1:0]. Luma timing adjust allows Control the user to specify a timing difference between chroma and luma samples. Reserved. CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and ...

Page 79

Subaddress Register Bit Description 0x2D Chroma CMG[11:8]. Chroma manual gain can Gain be used to program a desired Control 1 manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved. CAGT[1:0]. Chroma automatic gain ...

Page 80

ADV7181B Subaddress Register Bit Description 0x34 HS Position HSE[10:8]. HS end allows the Control 1 positioning of the HS output within the video line. Reserved. HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved. ...

Page 81

Subaddress Register Bit Description 0x39 PAL Comb YCMP[2:0]. Luma comb mode, PAL. Control CCMP[2:0]. Chroma comb mode, PAL. CTAPSP[1:0]. Chroma comb taps, PAL. 0x3A Reserved. PWRDN_ADC_2. Enables power- down of ADC2. PWRDN_ADC_1. Enables power- down of ADC1. PWRDN_ADC_0. Enables power- ...

Page 82

ADV7181B Subaddress Register Bit Description 0x41 Resample Reserved. Control SFL_INV. Controls the behavior of the PAL switch bit. Reserved. 0x48 Gemstar GDECEL[15:8]. See the Comments Control 1 column. 0x49 Gemstar GDECEL[7:0]. See the Comments Control 2 column. 0x4A Gemstar GDECOL[15:8]. ...

Page 83

Subaddress Register Bit Description 0x51 Lock Count CIL[2:0]. Count-into-lock determines the number of lines the system must remain in lock before showing a locked status. COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-of-lock before showing a ...

Page 84

ADV7181B Subaddress Register Bit Description 0x99 CCAP1 CCAP1[7:0] (Read Only) Closed caption data register. 0x9A CCAP2 CCAP2[7:0] (Read Only) Closed caption data register. 0x9B Letterbox 1 LB_LCT[7:0] (Read Only) Letterbox data register. 0x9C Letterbox 2 LB_LCM[7:0] (Read Only) Letterbox data ...

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Subaddress Register Bit Description 0xC4 ADC ADC2_SW[3:0]. Manual muxing SWITCH 2 control for ADC2. Reserved. ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. 0xDC Letterbox LB_TH[4:0]. Sets the threshold value Control 1 that determines if a line is black. ...

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ADV7181B Subaddress Register Bit Description 0xE6 NTSC V Bit NVEND[4:0]. How many lines after End l rollover to set V low. COUNT NVENDSIGN. NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V ...

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Subaddress Register Bit Description 0xF4 Drive DR_STR_S[1:0]. Select the drive Strength strength for the Sync output signals. DR_STR_C[1:0]. Select the drive strength for the Clock output signal. DR_STR[1:0]. Select the drive strength for the data output signals. Can be increased ...

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ADV7181B PROGRAMMING EXAMPLES EXAMPLES FOR 28 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 86. Mode 1 CVBS Input ...

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Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 87. Mode 2 S-Video Input Register Address Register Value 0x00 0x06 0x15 0x00 0x1D ...

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ADV7181B Mode 3 525i/625i YPrPb Input (Y on AIN1 AIN3, and Pb on AIN5) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 88. Mode 3 YPrPb Input 525i/625i Register Address Register ...

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Mode 4 CVBS Tuner Input CVBS PAL on AIN6 All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 89. Mode 4 Tuner Input CVBS PAL Only Register Address Register Value 0x00 0x80 0x07 0x01 ...

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ADV7181B EXAMPLES FOR 27 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 90. Mode 1 CVBS Input Register Address Register Value 0x15 ...

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Mode 3 525i/625i YPrPb Input (Y on AIN1 AIN3, and Pb on AIN5) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 92. Mode 3 YPrPb Input 525i/625i Register Address Register Value ...

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ADV7181B Mode 4 CVBS Tuner Input CVBS PAL on AIN6 All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 92. Mode 4 Tuner Input CVBS PAL Only Register Address Register Value 0x00 0x80 0x07 ...

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PCB LAYOUT RECOMMENDATIONS The ADV7181B is a high precision, high speed mixed-signal device. To achieve the maximum performance from the part important to have a PCB board with a good layout. The following is a guide for designing ...

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ADV7181B DIGITAL INPUTS The digital inputs on the ADV7181B are designed to work with 3.3 V signals, and are not tolerant signals. Extra compo- nents are needed logic signals are required to be applied ...

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TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7181B video decoder are shown in Figure 44 and Figure 45. For a detailed schematic diagram for the ADV7181B, refer to the ADV7181B evaluation note. Figure 44. ADI Recommended Antialiasing Circuit ...

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ADV7181B DVDDIO AGND DGND S-VIDEO ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS FILTER CIRCUIT ANTI-ALIAS Y FILTER CIRCUIT ANTI-ALIAS Pr FILTER CIRCUIT ANTI-ALIAS Pb FILTER CIRCUIT ANTI-ALIAS CBVS FILTER CIRCUIT RECOMMENDED ANTI-ALIAS FILTER CIRCUIT IS SHOWN IN FIGURE 44 ON THE PREVIOUS PAGE. ...

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OUTLINE DIMENSIONS 9.00 BSC SQ PIN 1 INDICATOR TOP VIEW 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 0.80 0.50 BSC SEATING PLANE 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW 0.60 MAX 0.60 MAX 49 48 8.75 ...

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ADV7181B ORDERING GUIDE 1 Model Temperature Range ADV7181BBCPZ 2 –40°C to +85°C 2 ADV7181BBSTZ –40°C to +85°C EVAL-ADV7181BEB 1 The ADV7181B is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on ...

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