HSDL-7000 Lite-On Electronics, HSDL-7000 Datasheet
HSDL-7000
Specifications of HSDL-7000
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HSDL-7000 Summary of contents
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... The HSDL-7000 is comprised of two state machines – the serial IR encode and the serial IR decode blocks. Each of these blocks derives their timing from the 16XCLK input signal from the UART. The Encode block is driven by the negative edge triggered TXD signal from the UART ...
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Pin Description 16XCLK - Positive edge triggered input clock that is set to 16 times the data transmission baud rate. The encode and decode schemes require this signal. The signal is usually tied to a UART’s BAUDOUT signal. TXD - ...
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Encoding Scheme 16 CLOCK CYCLES 16 X CLOCK TXD 7 cs IRTXD 3 cs The encoder sends a pulse for every space or “0” that is sent on the TXD line high to low transition of the TXD ...
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Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Output Current Power Dissipation Input/Output Voltage Power Supply Voltage Switching Specifications ( Volts 10 - Parameter Symbol Toggle Frequency Propagation Delay Time Output ...
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... The Minimum Pulse Width represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should (1/1.8432 MHz) or 1.63 s. The minimum pulse width specified for the HSDL-7000 is 250 ns, which is within IrDA specification. Under normal circumstances, the pulse width should not be less than 1.63 s. ...
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