CS493105-CLZ Cirrus Logic Inc, CS493105-CLZ Datasheet
CS493105-CLZ
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CS493105-CLZ Summary of contents
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Multi-Standard Audio Decoder Family Features CS4930X: DVD Audio Sub-family — PES Layer decode for A/V sync — DVD Audio Pack Layer Support — Meridian Lossless Packing Specification (MLP)™ — Dolby Digital™, Dolby Pro Logic II™ — MPEG-2, Advanced Audio Coding ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 7 1.1 Specified Operating Conditions .................................................................................. 7 1.2 Absolute Maximum Ratings ........................................................................................ 7 1.3 Thermal Data .............................................................................................................. 7 1.4 Digital D.C. Characteristics ......................................................................................... 8 1.5 Power Supply Characteristics ..................................................................................... 8 1.6 Switching ...
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Internal Boot ............................................................................................................. 63 8.5 Application Failure Boot Message ............................................................................ 63 8.6 Resetting the CS493XX ............................................................................................ 63 8.7 External Memory Examples ...................................................................................... 64 8.7.1 Non-Paged Autoboot Memory ...................................................................... 64 8.7.2 32 Kilobyte Paged Autoboot Memory ........................................................... 65 8.8 CDB49300-MEMA.0 ...
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Figure 18. Motorola Figure 19. SPI Write Flow Diagram ...................................................................................... 37 Figure 20. SPI Read Flow Diagram ...................................................................................... 37 Figure 21. SPI Timing ........................................................................................................... 39 Figure 22. I2C® Write Flow Diagram .................................................................................... 40 Figure 23. I2C® Read Flow Diagram ...
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Table 20. Input SCLK Polarity Configuration (Input Parameter C) .............................................................................................. 77 Table 21. Input FIFO Setup Configuration (Input Parameter D) .............................................................................................. 77 Table 22. Output Clock Configuration (Parameter A) ....................................................................................................... 78 Table 23. Output Data Format Configuration (Parameter B) ....................................................................................................... ...
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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this ...
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CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C.) A 1.1. Specified Operating Conditions (AGND, ...
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Digital D.C. Characteristics (VA, VD[3:1] = 2.5 V ±5%; measurements performed under static conditions.) Parameter High-level input voltage Low-level input voltage High-level output voltage –2 Low-level output voltage 2 ...
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Switching Characteristics — (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter RESET minimum pulse width low (-CL) RESET minimum pulse width low (-IL) All bidirectional pins high-Z after RESET low ...
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Switching Characteristics — Intel (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter Address setup before CS and RD low or CS and WR low Address hold time after CS and ...
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A1:0 DATA7:0 T ias CS T icdr Figure 3. Intel A1:0 T iah DATA7:0 T ias CS T icdw RD WR Figure 4. Intel DS339F7 idhr T idd T idis T T irpw ...
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Switching Characteristics — Motorola (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter Address setup before CS and DS low Address hold time after CS and DS low Delay between DS ...
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A1:0 T mah DATA7:0 T mas CS T mrwsu T R/W DS Figure 5. Motorola A1 A7 Figure 6. Motorola DS339F7 T mdhr T mdd T mcdr mdis T ...
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Switching Characteristics — SPI™ Control Port (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter SCCLK clock frequency CS falling to SCCLK rising Rise time of SCCLK line Fall time of ...
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DS339F7 CS49300 Family DSP 15 ...
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Switching Characteristics — I 1.11. (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter SCCLK clock frequency Bus free time between transmissions Start-condition hold time (prior to first clock pulse) Clock low ...
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DS339F7 CS49300 Family DSP 17 ...
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Switching Characteristics — Digital Audio Input (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter SCLKN1(2) period for both Master and Slave mode SCLKN1(2) duty cycle for Master and Slave mode ...
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SCLKN1 SCLKN2 LRCLKN1 LRCLKN2 SDATAN1 SDATAN2 SCLKN1 SCLKN2 LRCLKN1 LRCLKN2 SDATAN1 SDATAN2 Figure 9. Digital Audio Input Data, Master and Slave Clock Timing DS339F7 CS49300 Family DSP MASTER MODE T lrds T sclki T T sdsum sdhm SLAVE MODE T ...
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Switching Characteristics — Serial Bursty Data Input (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter Serial compressed data clock CMPCLK period CMPDAT setup before CMPCLK high CMPDAT hold after CMPCLK ...
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Switching Characteristics — Parallel Data Input (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter CMPCLK Period DATA[7:0] setup before CMPCLK high DATA[7:0] hold after CMPCLK high Delay from falling edge ...
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Switching Characteristics — Digital Audio Output (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C Parameter MCLK period MCLK duty cycle SCLK period for Master or Slave mode SCLK duty cycle for ...
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MCLK (Input) SCLK (Output) MCLK (Output) SCLK (Output) AUDATA2:0 AUDATA2:0 Figure 12. Digital Audio Output Data, Input and Output Clock Timing DS339F7 T sdmi T sdmo MASTER MODE SCLK T sclk T lrds LRCLK T adsm SLAVE MODE SCLK T ...
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FAMILY OVERVIEW The CS49300 family contains system on a chip solutions for multichannel audio decompression and digital signal processing. The CS49300 family is split into 4 sub-families targeted at the DVD, broadcast and audio/video receiver (AVR), and effects and ...
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DTS Virtual 5.1 Versions) ™ • SRS Circle Surround I/II ® • HDCD • Cirrus P.D.F. (Dolby Pro Logic 2Fs Decoder and PCM Upsampler) • Cirrus PL2_2FS (Dolby Pro Logic II 2Fs Decoder and PCM Upsampler) Please refer to ...
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MPEG Multichannel, MP3, decoder or PCM effects processor or mixer, or for car audio applications. Typical applications will include multichannel amplifiers, outboard pre-amplifiers, HDTVs ...
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TYPICAL CONNECTION DIAGRAMS Six typical connection diagrams have been presented to illustrate using the part with the different communication modes available. They are as follows: 2 ® Figure 13, "I C Control" on page 29 2 ® Figure 14, ...
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Due to the internal, multiplexed design of the pins, certain signals may or may not require termination depending on the mode being used parallel host communication mode is not being used, GPIO[11:0] must be terminated or driven as ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2.5VA + 1 uF ...
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Supply (+2.5VD) SYSTEM CONTROLLER / OCTAL F/F OCTAL F/F A[15:8] Q[7:0] Q[7:0] D[7:0] D[7:0] A[7:0] D[7:0] Figure 14 ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2.5VA + 1 uF ...
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Supply (+2.5VD) SYSTEM CONTROLLER / OCTAL F/F OCTAL F/F A[15:8] Q[7:0] Q[7:0] D[7:0] D[7:0] A[7:0] D[7:0] Figure 16. SPI Control ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2. ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2.5VA + + 1 ...
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POWER The CS493XX requires a 2.5V digital power supply for the digital logic within the DSP and a 2.5V analog power supply for the internal PLL. There are three digital power pins, VD1, VD2 and VD3, along with three ...
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CONTROL Control of the CS493XX can be accomplished through one of four methods. The CS493XX 2 ® supports I C and SPI serial communication. In addition the CS493XX supports both a Motorola and Intel byte wide parallel host control ...
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SPI START: CS (LOW) WRITE ADDRESS BYTE WITH MODE BIT SET TO 0 FOR WRITE SEND DATABYTE MORE DATA (HIGH) Figure 19. SPI Write Flow Diagram 4) When all of the bytes have been transferred, chip select should ...
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After the falling edge of the serial control clock (SCCLK) for the read/write bit, the data is ready to be clocked out on the control data out pin (CDOUT). Data ...
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DS339F7 CS49300 Family DSP 39 ...
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The 0x00 byte represents the 7 bit of address (0000000b) and the read/write bit set designate a write. 3) After each byte (including the address and each data byte) the host must release the ...
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SCCLK and data transitions occur on the falling edge of SCCLK INTREQ is still low after a byte transfer, an acknowledge (SCDIO clocked low by SCCLK) must be sent ...
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CS49300 Family DSP DS339F7 ...
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In general, when communicating CS493XX, INTREQ will not go low unless the host first sends a read request command message. In other words the host must solicit a response from the DSP. In this environment, the host must read from ...
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When using automated communication ports, however, the host is often limited to sampling the status of INTREQ after an entire byte has been transferred. In this situation a low-high-low transition (case 3) would be missed and the host will see ...
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Motorola and Intel sections. The following will be covered: Host Message (HOSTMSG) Register, A[1:0] = 00b 7 6 HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG7–0 Host data to ...
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Intel Parallel Host Communication Mode The Intel parallel host communication mode is implemented using the pins given in The INTREQ pin is controlled by the application code when a parallel host communication mode has been selected. When the code ...
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The flow diagram shown in Figure 25 sequence of events that define a one-byte read in Intel mode. The protocol presented in will now be described in detail. 1) The host must first drive the A1 and A0 register address ...
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CMPDATA: The host indicates that this is a write cycle by driving the R/W pin low. 2) The host initiates a write cycle by driving the CS and DS pins low. 3) The host drives the data byte to the ...
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Read_Byte_MOT() or Read_Byte_INT(), and ‘Write_Byte_*()’ generic reference to Write_Byte_MOT() or Write_Byte_INT(). shows a typical write sequence. The protocol presented in Figure 28 will now be described in detail. 1) When the host is communicating with the CS493XX, ...
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INTREQ = 0 YES READ_BYTE_*(HOST CONTROL REGISTER) HOUTRDY==1 YES READ_BYTE_*(HOST MESSAGE REGISTER) YES MORE BYTES TO READ? NO WAIT 100 uS READ_BYTE_*(HOST CONTROL REGISTER) HOUTRDY==1 NO FINISHED Figure 29. Typical Parallel Host Mode Control Read Sequence Flow Diagram 50 the ...
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EXTERNAL MEMORY If using one of the serial modes, i.e. SPI or I system designer has the option of using external memory. The external memory interface is not compatible with the parallel modes since there are shared pins that ...
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Paged Memory Sometimes it is desirable for the external memory to be ...
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EMAD[7:0] CS493XX EXTMEM EMOE EMWR EMAD7:0 Figure 31. External Memory Read (16-bit address) EXTMEM EMOE EMWR EMAD7:0 Figure 32. External Memory Write (16-bit address) DS339F7 3.3V ...
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BOOT PROCEDURE & RESET In this section the process of booting and downloading to the CS493XX will be covered as well as how to perform a soft reset. Host boot and autoboot and reset are covered in this section. ...
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RESET(LOW) (NOTE 1) WRITE_*(DOWNLOAD_ BOOT, MSG_SIZE) N INTREQ LOW? Y READ_*(MESSAGE) N MESSAGE == BOOTSTART? Y WRITE_*(.LD FILE, DOWNLOAD FILE SIZE) N INTREQ LOW? Y READ_*(MESSAGE) N MESSAGE == BOOT_SUCCESS? Y WRITE_*(BOOT_ SUCCESS_RECEIVED, MSG-SIZE) WAIT 5 MS (NOTE 4) WRITE_*(HW_CONFIG_MSG, ...
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RESET(LOW) (NOTE 1) READ HOSTCTL REGISTER N HOUTRDY LOW? Y READ_*(MESSAGE) N MESSAGE == BOOTSTART? Y WRITE_*(.LD FILE, DOWNLOAD FILE SIZE) READ HOSTCTL REGISTER N HOUTRDY LOW? Y READ_*(MESSAGE) N MESSAGE == BOOT_SUCCESS? Y WRITE_*(BOOT_ SUCCESS_RECEIVED, MSG-SIZE) WAIT 5 MS ...
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The host should re-try steps 1 through 3 and if failure is met again, the serial communication timing and protocol should be inspected. 5) After receiving the BOOT_START byte, the host should write the downloadable ...
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The timing for an autoboot sequence is illustrated in Figure 35. The sequence is initiated by driving RESET low and placing the decoder into reset. At the rising edge of RESET, the ABOOT, WR, and RD pins are sampled. If ...
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RESET(LOW) (NOTE 1) ABOOT(LOW) RESET(HIGH) (NOTE 2) RELEASE ABOOT WAIT 200 MS (NOTE 3) READ_*(VARIABLE) (NOTE 4) N CORRECT VALUE? Y AUTOBOOT COMPLETE WRITE_*(HW_CONFIG_MSG, HW_MSG_SIZE) (NOTE 4) WRITE_*(SW_CONFIG_MSG, SW_MSG_SIZE) (NOTE 4) WRITE_*(KICKSTART, MSG_SIZE) (NOTE 4) DS339F7 WAIT 5 MS Notes: ...
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Configuration” on page The software configuration messages are specific to each application. The software user’s guides (AN163, AN163x, AN162, AN162x) for each application code provides a list ...
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Decreasing Autoboot Times Using GFABT Codes (Fast Autoboot) Instead the host toggling the RESET line while ABOOT is held low, the host decrease the Autoboot download time by instead downloading a special code called “GFABT” (Genesis Autoboot) which first ...
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RESET(LOW) (NOTE 1) WRITE_*(DOWNLOAD_ BOOT, MSG_SIZE) N INTREQ LOW? Y WRITE_*(GFABTX.LD FILE, DOWNLOAD FILE SIZE) WAIT 135 MS, 100 MS (NOTE 5) READ_*(VARIABLE) (NOTE 4) N CORRECT VALUE? Y AUTOBOOT COMPLETE WRITE_*(HW_CONFIG_MSG, HW_MSG_SIZE) (NOTE 6) WRITE_*(SW_CONFIG_MSG, SW_MSG_SIZE) ...
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Design Considerations when using GFABT Codes The designer should be aware that the gfabt codes do not lock the PLL, so therefore the actual time involved with autobooting is subject to the open loop VCO frequency. The PLL is ...
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This method of resetting the DSP is usually referred “soft reset” even though it involves toggling the reset pin. Table 12 lists ...
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ROM Content CS493254 N/A, All IBA codes are loaded using Host Boot technique Dolby Digital with PLII + Cinema Re-EQ, HDCD CS493264 N/A, All IBA codes are loaded using Host Boot technique Dolby Digital with C.E.S., MPEG Multichannel with C.E.S., ...
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Dolby Digital with Pro Logic II with Cirrus Extra Surround 0x07FFF 0x08000 MPEG Multichannel with Pro Logic II 0x0FFFF 0x10000 DTS-ES Extended Surround 0x17FFF 0x18000 DTS-ES Neo:6 0x1FFFF 0x20000 HDCD 0x27FFF 0x28000 LOGIC7 0x2FFFF 0x30000 MP3 0x37FFF 0x38000 Virtual ...
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DS339F7 CS49300 Family DSP ...
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HARDWARE CONFIGURATION After download or soft reset, and before kickstarting the application (please see the Audio Manager in the Application Messaging Section of any Application Code User’s Guide for more information on kickstarting), the host has the option of ...
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DIGITAL INPUT & OUTPUT The CS493XX supports a wide variety of data input and output mechanisms through various input and output ports. Hardware availability is entirely dependent on whether the software application code being used supports the required mode. ...
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Digital Audio Input Port The digital audio input port, or DAI, is used for both compressed and PCM digital audio data input. In addition this port supports a special clocking mode in which a clock can be input to ...
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If using I2C or SPI control, then parallel delivery can still be used using CMPCLK and GPIO[7:0]. 10.4.1.Parallel Delivery with Parallel Control If using the Intel or Motorola Parallel host interface mode, the system designer can also choose ...
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Digital Audio Output Port The Digital Audio Output port, or DAO, is the port used for digital output from the DSP. shows the signals associated with the DAO. As with the input ports the clocks and data are fully ...
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Please consult the application code user’s guides to determine what modes are supported by the application code being used. 10.5.1.IEC60958 Output The XMT958 output is shared with the AUDATA3 output so only one can be used at any one time. ...
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HARDWARE CONFIGURATION After download or soft reset, and before kickstarting the application (please see the Audio Manager in the Application Messaging Section of any application code user’s guide for more information on kickstarting), the host has the option of ...
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A Value Data Type 0 DAI - PCM (default) CDI - Compressed 1 DAI - PCM and Compressed CDI - Unused 2 DAI - Unused CDI - PCM 3 DAI - PCM CDI - Bursty Compressed (for Broadcast-based Application Codes ...
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B Value Data Format 2 2 PCM - I S 24-bit Multichannel PCM (6 Channel) - Left Justified 24-bit PCM (for Post-Processing Codes that can accept 6 channels on one line like THX Surround EX application code PCM ...
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B Value Data Format 84 PCM - Left Justified 24-bit Multichannel PCM (4 Channel) - Left Justified 20-bit (used only by special post-processing application codes) Table 19. Input Data Format Configuration (Input Parameter B) (Continued) SCLK Polarity (Both CDI & ...
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Output Data Hardware Configuration The naming convention for the DAO configuration is as follows: OUTPUT where the parameters are defined as DAO Mode (Master/Slave for LRCLK and SCLK Data Format ...
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DAO Data Format Of AUDATA0 (or AUDATA0 B Value for Multichannel Modes) 22 Multichannel (2 channel) 20-bit Left Justified (SCLK must be at least 128Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in ...
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Output Configuration Considerations 1) All PCM output is 24-bit resolution 2) An SCLK frequency of at least 128Fs must be selected for the 20-bit multichannel (6 channel) mode SCLK frequency of at least 128Fs must be selected ...
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WORD# VALUE WORD# 1 0x800210 12 2 0x3FBFC0 13 3 0x800110 14 4 0xC0002C 15 5 0x800217 16 6 0x8080FF 17 7 0x80021A 18 8 0x8080FF 19 9 0x800117 20 10 0x001000 21 11 0x80011A 22 Table 27. Example Values ...
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PIN DESCRIPTIONS AUDATA3, XMT958 WR,DS,EMWR,GPIO10 RD,R/W,EMOE,GPIO11 A1, SCDIN A0, SCCLK DATA7,EMAD7,GPIO7 DATA6,EMAD6,GPIO6 DATA5,EMAD5,GPIO5 DATA4,EMAD4,GPIO4 DATA3,EMAD3,GPIO3 DATA2,EMAD2,GPIO2 DATA1,EMAD1,GPIO1 DATA0,EMAD0,GPIO0 SCDIO, SCDOUT,PSEL,GPIO9 ABOOT, INTREQ EXTMEM, GPIO8 VA—Analog Positive Supply: Pin 34 Analog positive supply for clock generator. Nominally +2.5 V. AGND—Analog ...
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CLKSEL—DSP Clock Select: Pin 31 This pin selects the clock mode of the CS493XX. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal clocks are derived. When CLKSEL is high CLKIN is connected to ...
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RESET—Master Reset Input: Pin 36 Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS493XX and to guarantee that the device is not active during initial power-on stabilization periods. At the rising edge of reset ...
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SCLK—Audio Output Bit Clock: Pin 43 Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and ...
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CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29 When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital- audio frame clock that is an output in master mode and an input in ...
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... DS339F7 I D (Industrial) (Automotive) ° ° ° ° CS493292-IL CS493302-IL CS493263-IL CS493263-DL (Pb-free Only) CS493254-IL CS493264-IL CS49300 Family DSP Pb-free Option Package “Z” Suffix CS493122-CLZ CS493292-CLZ CS493302-CLZ or -ILZ CS493253-CLZ CS493263-CLZ or -ILZ or -DLZ 44-pin PLCC CS493254-CLZ CS493264-CLZ CS493005-CLZ CS493105-CLZ CS493115-CLZ CS493295-CLZ 87 ...
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PACKAGE DIMENSIONS 44L PLCC PACKAGE DRAWING DIM MIN A 0.165 A1 0.090 B 0.013 D 0.685 D1 0.650 D2 0.590 E 0.685 E1 0.650 E2 0.590 e 0.040 INCHES MAX 0.180 0.120 0.021 0.695 ...
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DOCUMENT REVISIONS Revision Date PP4 Mar 2003 F1 Feb 2004 F2 Apr 2004 F3 APR 2005 F4 JUN 2005 F5 NOV 2005 F6 JAN 2006 F7 APR 2006 DS339F7 Last preliminary release. Initial final release. 1. p.73, Corrected Hex ...
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CS49300 Family DSP DS339F7 ...