MCP25055T-I/SL Microchip Technology, MCP25055T-I/SL Datasheet - Page 19

• Manufacturer Part Number: MCP25055T-I/SL
• Description: IC I/O EXPANDER CAN 8B 14SOIC
• Manufacturer: Microchip Technology

Specifications of MCP25055T-I/SL

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Interface: 1-Wire, CAN
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 4MHz
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: ADC, Memory, PWM
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MCP25055TI/SL

3.0
3.1
The MCP2502X/5X allows the user to pre-program
registers pertaining to CAN module and device
configuration into non-volatile EPROM memory. In this
way, the device is initialized to a default state after
power-up. The user registers are transferred to SRAM
during the power-up sequence and many of the
registers are able to be accessed via the CAN bus once
the device establishes a connection with the bus.
Additionally, there are 16 user-defined registers that
can be used to store information about the part (e.g.,
serial number, node identifier, etc.). The registers are
summarized in Table 3-1.
TABLE 3-1:
© 2007 Microchip Technology Inc.
Note 1:
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
2:
3:
4:
USER REGISTERS
Description
PWM1DCH PWM1 Duty Cycle (DC) MSBs
PWM2DCH PWM2 Duty Cycle (DC) MSBs
OPTREG1
GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.
User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”
commands.
Cannot be modified from initial programmed values.
Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).
IOINTPO
IOINTEN
T1CON
T2CON
CNF1
CNF2
CNF3
GPLAT
Name
0xFF
PR1
PR2
USER MEMORY MAP
3
3
3
Enable inputs for Transmit-On-Change
feature
Defines polarity for I/O or greater than/
less than operator for A/D Transmit-On-
Change inputs
General Purpose I/O (GPIO) Register
Reserved
Configuration options, including GPIO
pull-up enable, clockout enable and
prescaler
PWM1 Timer Control Register; contains
enable bit, clock prescale and DC LSBs
PWM2 Timer Control Register; contains
enable bits, clock prescale and DC LSBs
PWM1 Period Register
PWM2 Period Register
CAN module register configures
synchronization jump width and baud rate
prescaler
CAN module register configures
propagation segment, phase segment 1,
and determines number of sample points
CAN module register configures phase
buffer segment 2, Sleep mode
Description
Address
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
Note 1: When transferred to RAM, the register
TXID0SIDH Transmit Buffer 0, Standard ID MSB
TXID1SIDH Transmit Buffer 1, Standard ID MSB
TXID2SIDH Transmit Buffer 2, Standard ID MSB
2: Do not address locations outside of the
RXF1SIDH
TXID0SIDL
TXID0EID8
TXID0EID0
TXID1SIDL
TXID1EID8
TXID1EID0
RXF0EID0
RXF1SIDL
RXF1EID8
RXF1EID0
Name
addresses are offset by 1Ch. Accessing
individual registers using the “Write
Register” or “Read Register command
requires use of the offset address. Also,
see
accessible registers not contained in user
EPROM.
user memory map or unexpected results
may occur.
MCP2502X/5X
Table 3-2
Acceptance Filter 0, Extended ID
LSB
Acceptance Filter 1, Standard ID
MSB
Acceptance Filter 1, Standard ID
LSB, Extended ID USB, and
Extended ID enable
Acceptance Filter 1, Extended ID
MSB
Acceptance Filter 1, Extended ID
LSB
Transmit Buffer 0, Standard ID LSB,
Extended ID USB, and Extended ID
enable
Transmit Buffer 0, Extended ID MSB
Transmit Buffer 0, Extended ID LSB
Transmit Buffer 1, Standard ID LSB,
Extended ID USB, and Extended ID
enable
Transmit Buffer 1, Extended ID MSB
Transmit Buffer 1, Extended ID LSB
for
Description
DS21664D-page 19
information
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