MCP25055T-I/SL Microchip Technology, MCP25055T-I/SL Datasheet - Page 20

• Manufacturer Part Number: MCP25055T-I/SL
• Description: IC I/O EXPANDER CAN 8B 14SOIC
• Manufacturer: Microchip Technology

Specifications of MCP25055T-I/SL

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Interface: 1-Wire, CAN
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 4MHz
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: ADC, Memory, PWM
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MCP25055TI/SL

MCP2502X/5X
TABLE 3-1:
TABLE 3-2:
DS21664D-page 20
Note 1:
Address
1Fh**
Addr*
18h
19h
1Ah
50h
51h
52h
53h
54h
55h
56h
57h
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
2:
3:
4:
*
**
ADRES3H
ADRES2H
ADRES1H
ADRES0H
ADRES3L
ADRES2L
ADRES1L
ADRES0L
RXF0SIDH Acceptance Filter 0, Standard ID MSB
GPDDR
OPTREG2
RXF0SIDL
RXF0EID8
ADCON0
ADCON1
RXMSIDH
GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.
User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”
commands.
Cannot be modified from initial programmed values.
Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).
These addresses are used when using the “Write Register” or “Read Register” command
The GPDDR register is not offset to RAM the same as the other registers in the EPROM
RXMSIDL
RXMEID8
RXMEID0
Name
EFLG
REC
STCON
TEC
Name
—
—
ACCESSIBLE RAM REGISTERS NOT IN THE EPROM MAP
USER MEMORY MAP (CONTINUED)
4
4
AN3.9
AN3.1
AN2.9
AN2.1
AN1.9
AN1.1
AN0.9
AN0.1
ESCF
A/D Control Register; contains enable,
conversion rate, channel select bits
A/D Control Register; contains voltage
reference source, conversion rate and
A/D input enable bits
Scheduled Transmission Control Register
Configuration options, including Sleep
mode, RTR message and error recovery
enables
Reserved
Reserved
Acceptance Filter Mask, Standard ID MSB
Acceptance Filter Mask, Standard ID LSB
and Extended ID USB
Acceptance Filter Mask, Extended ID
MSB
Acceptance Filter Mask, Extended ID LSB
Acceptance Filter 0, Standard ID LSB,
Extended ID USB, and Extended ID
enable
Acceptance Filter 0, Extended ID MSB
bit7
—
AN3.8
AN3.0
AN2.8
AN2.0
AN1.8
AN1.0
AN0.8
AN0.0
DDR6
RBO
bit6
Description
DDR4
AN3.6
AN2.6
AN1.6
AN0.6
TXEP
bit5
—
—
—
—
Transmit Error Counters
Receive Error Counters
AN3.6
AN2.6
AN1.6
AN0.6
DDR4
TXEP
bit4
—
—
—
—
Address
35-44h
DDR3
RXEP
AN3.5
AN2.5
AN1.5
AN0.5
bit3
—
—
—
—
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
TXWAR
ADCMP3H
ADCMP2H
ADCMP1H
ADCMP0H
ADCMP3L
ADCMP2L
ADCMP1L
ADCMP0L
USER[0:F]
TXID2SIDL
TXID2EID8
TXID2EID0
AN3.4
AN2.4
AN1.4
AN0.4
DDR2
bit2
GPDDR
—
—
—
—
Name
1
RXWAR
4
4
4
4
2
4
4
4
4
DDR1
AN3.3
AN2.3
AN1.3
AN0.3
bit1
—
—
—
—
Transmit Buffer 2, Standard ID LSB,
Extended ID USB, and Extended ID
enable
Transmit Buffer 2, Extended ID MSB
Transmit Buffer 2, Extended ID LSB
Analog Channel 3 Compare Value
MSB
Analog Channel 3 Compare Value
LSb’s
Analog Channel 2 Compare Value
MSB
Analog Channel 2 Compare Value
LSb’s
Analog Channel 1 Compare Value
MSB
Analog Channel 1 Compare Value
LSb’s
Analog Channel 0 Compare Value
MSB
Analog Channel 0 Compare Value
LSb’s
General Purpose I/O Data Direction
Register
User Defined Bytes (0-15)
© 2007 Microchip Technology Inc.
EWARN
AN3.2
AN2.2
AN1.2
AN0.2
DDR0
bit0
—
—
—
—
Description
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Value on
-111 1111
xx-- ----
xx-- ----
xx-- ----
xx-- ----
POR
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Value on
-111 1111
uu-- ----
uu-- ----
uu-- ----
uu-- ----
RST