MCP25055T-I/SL Microchip Technology, MCP25055T-I/SL Datasheet - Page 9

• Manufacturer Part Number: MCP25055T-I/SL
• Description: IC I/O EXPANDER CAN 8B 14SOIC
• Manufacturer: Microchip Technology

Specifications of MCP25055T-I/SL

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Interface: 1-Wire, CAN
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 4MHz
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: ADC, Memory, PWM
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MCP25055TI/SL

As a result of resynchronization, PS1 may be
lengthened or PS2 may be shortened. The amount of
lengthening or shortening of the phase buffer segments
has an upper-bound given by the SJW. The SJW is
programmable between 1 T
the SJW will be added to PS1 (or subtracted from PS2)
depending on the phase error (e) of the edge in relation
to the receiver’s SyncSeg. The phase error is defined
as follows:
• e = 0 if the edge lies within SYNCESEG
• e > 0 if the edge lies before the sample point
• e < 0 if the edge lies after the sample point of the
2.4.6
There are three registers (in the configuration register
module) associated with the CAN bit timing logic that
controls the bit timing for the CAN bus interface.
2.4.6.1
The BRP<5:0> bits control the baud rate prescaler.
These bits set the length of T
input frequency, with the minimum length of T
2 T
The SJW<1:0> bits select the synchronization jump
width in terms of number of T
REGISTER 2-3:
© 2007 Microchip Technology Inc.
- No resynchronization is required.
- PS1 will be lengthened by the amount of the
previous bit and before the SyncSeg of the
current bit
- PS2 will be shortened by the amount of the
OSC
SJW.
SJW.
in length (when BRP<5:0> are set to 000000).
bit 7-6
bit 5-0
CONFIGURATION REGISTERS
CNF1
CNF1 - CAN CONFIGURATION REGISTER 1
SJW1:SJW0: Synchronized Jump Width bits
11 = Length = 4 x T
10 = Length = 3 x T
01 = Length = 2 x T
00 = Length = 1 x T
BRP5:BRP0: Baud Rate Prescaler bits
111111 =
-
-
000000 =
bit 7
Legend:
R = Readable bit
- n = Value at POR
R/W-0
SJW1
Q
Q
and 4 T
’s.
Q
relative to the OSC1
T
T
Q
Q
= 2 x 64 x 1/F
= 2 x 1 x 1/F
R/W-0
SJW0
Q
. The value of
Q
Q
Q
Q
Q
OSC
being
R/W-0
OSC
BRP5
W = Writable bit
‘1’ = Bit is set
R/W-0
BRP4
2.4.6.2
The PRSEG<2:0> bits set the length (in T
propagation segment. The PS1<2:0> bits set the length
(in T
many times the RXCAN pin is sampled. Setting this bit
to a ‘1’ causes the bus to be sampled three times.
Twice at T
normal sample point (which is at the end of PS1). The
value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, the RXCAN pin is sampled only once at the
sample point. The BTLMODE bit controls how the
length of PS2 is determined. If this bit is set to a ‘1’, the
length of PS2 is determined by the PS2<2:0> bits of
CNF3. If the BTLMODE bit is set to a ‘0’ then the length
of PS2 is the greater of PS1 and the information
processing time (which is fixed at 2 T
MCP2502X/5X).
2.4.6.3
The PS2<2:0> bits set the length, in T
CNF2.BTLMODE bit is set to a ‘1’. If the BTLMODE bit
is set to a ‘0’, the PS2<2:0> bits have no effect.
Additionally, the wake-up filter (CNF3.WAKFIL) is
implemented in the CNF3 register. This filter is a low-
pass filter that can be used to prevent the MCP2502X/
5X from waking up due to short glitches on the CAN
bus.
Q
’s) of phase segment 1. The SAM bit controls how
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BRP3
Q
/2 before the sample point and once at the
CNF2
CNF3
MCP2502X/5X
R/W-0
BRP2
x = Bit is unknown
R/W-0
BRP1
Q
DS21664D-page 9
’s, of PS2, if the
Q
Q
’s) of the
R/W-0
BRP0
for the
bit 0