PCA9672PW,118 NXP Semiconductors, PCA9672PW,118 Datasheet - Page 17

IC I/O EXPANDER I2C 8B 16TSSOP

PCA9672PW,118

Manufacturer Part Number
PCA9672PW,118
Description
IC I/O EXPANDER I2C 8B 16TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9672PW,118

Package / Case
16-TSSOP
Interface
I²C
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
1MHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9672
Number Of Lines (input / Output)
8.0 / 8.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
400 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5.5 V
Logic Type
I/O Expander
Maximum Clock Frequency
1 MHz
Mounting Style
SMD/SMT
Number Of Input Lines
8.0
Number Of Output Lines
8.0
Output Current
50 mA
Output Voltage
5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935282747118
PCA9672PW-T
PCA9672PW-T
NXP Semiconductors
13. Dynamic characteristics
Table 6.
V
[1]
[2]
PCA9672_2
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing; C
t
t
t
Interrupt timing; C
t
t
Reset timing (see
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
v(D)
d(rst)
w(rst)
rec(rst)
rst
DD
= 2.3 V to 5.5 V; V
t
t
VD;ACK
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Parameter
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid acknowledge
time
data valid time
data set-up time
LOW period of the SCL
clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by the
input filter
data output valid time
data input setup time
data input hold time
data input valid time
reset delay time
reset pulse width
reset recovery time
reset time
Dynamic characteristics
L
[1]
100 pF (see
Figure
L
[6]
SS
100 pF (see
= 0 V; T
[2]
22)
Figure 12
amb
Figure 12
= 40 C to +85 C; unless otherwise specified.
Conditions
and
Remote 8-bit I/O expander for Fm+ I
Figure
and
Rev. 02 — 6 July 2007
Figure
[4][5]
13)
Standard mode
13)
Min
300
250
100
4.7
4.0
4.7
4.0
0.3
4.7
4.0
0
0
0
4
4
0
-
-
-
-
-
-
I
2
C-bus
1000
Max
3.45
100
300
50
4
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast mode I
Min
100
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
0
4
4
0
-
-
-
-
b
b
2
[3]
[3]
C-bus with interrupt and reset
2
C-bus
Max
400
300
300
0.9
50
4
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Fast mode Plus
0.26
0.26
0.26
0.05
0.26
Min
100
0.5
0.5
PCA9672
50
50
0
0
0
4
4
0
-
-
-
-
-
-
© NXP B.V. 2007. All rights reserved.
I
2
C-bus
1000
Max
0.45
450
120
120
50
4
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
17 of 27
Unit
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s

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