PCA9506DGG,518 NXP Semiconductors, PCA9506DGG,518 Datasheet
PCA9506DGG,518
Specifications of PCA9506DGG,518
PCA9506DGG-T
PCA9506DGG-T
Related parts for PCA9506DGG,518
PCA9506DGG,518 Summary of contents
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PCA9505/06 40-bit I Rev. 4 — 3 August 2010 1. General description The PCA9505/PCA9506 provide 40-bit parallel input/output (I/O) port expansion for 2 I C-bus applications organized in 5 banks of 8 I/Os supply voltage, the outputs ...
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... NXP Semiconductors Inputs: Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change Polarity Inversion register allows inversion of the polarity of the I/O pins when read Active LOW reset (RESET) input pin resets device to power-up default state ...
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... NXP Semiconductors 5. Block diagram SCL SDA V V RESET Fig 1. PCA9505_9506 Product data sheet PCA9505/PCA9506 LOW PASS INPUT FILTERS DD POWER-ON SS RESET All I/Os are set to inputs at power-up and RESET. Block diagram of PCA9505/06 All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 August 2010 ...
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... NXP Semiconductors write configuration Fig 2. PCA9505_9506 Product data sheet I/O configuration register data from D Q shift register CK Q pulse data from D Q shift register write pulse CK output port register read pulse data from shift register write polarity pulse On power-up or RESET, all registers return to default values. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. PCA9505_9506 Product data sheet SDA 1 SCL 2 3 IO0_0 4 IO0_1 IO0_2 IO0_3 7 8 IO0_4 9 IO0_5 IO0_6 IO0_7 12 13 IO1_0 14 IO1_1 PCA9505DGG PCA9506DGG IO1_2 15 IO1_3 16 IO1_4 IO1_5 IO1_6 20 IO1_7 21 IO2_0 IO2_1 IO2_2 25 IO2_3 Pin configuration for TSSOP56 All information provided in this document is subject to legal disclaimers. Rev. 4 — ...
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... NXP Semiconductors Fig 4. 6.2 Pin description Table 2. Symbol SDA SCL IO0_0 to IO0_7 IO1_0 to IO1_7 IO2_0 to IO2_7 IO3_0 to IO3_7 IO4_0 to IO4_7 PCA9505_9506 Product data sheet terminal 1 index area IO0_4 1 IO0_5 2 3 IO0_6 IO0_7 5 IO1_0 6 IO1_1 7 8 IO1_2 9 IO1_3 IO1_4 IO1_5 12 13 IO1_6 ...
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... NXP Semiconductors Table 2. Symbol OE INT RESET [1] HVQFN56 package die supply ground is connected to both V must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region ...
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... NXP Semiconductors The lowest 6 bits are used as a pointer to determine which register will be accessed. The registers are: • IP: Input Port registers (5 registers) • OP: Output Port registers (5 registers) • PI: Polarity Inversion registers (5 registers) • IOC: I/O Configuration registers (5 registers) • MSK: Mask interrupt registers (5 registers) If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically incremented after a read or write ...
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... NXP Semiconductors 7.3 Register definitions Table 3. Register summary Register # (hex) Input Port registers Output Port registers Polarity Inversion registers I/O Configuration registers PCA9505_9506 Product data sheet Symbol IP0 IP1 IP2 IP3 IP4 OP0 OP1 OP2 OP3 OP4 PI0 PI1 PI2 PI3 ...
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... NXP Semiconductors Table 3. Register summary …continued Register # (hex) Mask Interrupt registers 7.3.1 IP0 to IP4 - Input Port registers These registers are read-only. They reflect the incoming logic levels of the port pins regardless of whether the pin is defined as an input or an output by the I/O Configuration register ...
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... NXP Semiconductors 7.3.2 OP0 to OP4 - Output Port registers These registers reflect the outgoing logic levels of the pins defined as outputs by the I/O Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the values that are in the flip-flops controlling the output selection, not the actual pin values ...
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... NXP Semiconductors 7.3.4 IOC0 to IOC4 - I/O Configuration registers These registers configure the direction of the I/O pins. Cx[ The corresponding port pin is an output. Cx[ The corresponding port pin is an input. Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7). ...
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... NXP Semiconductors 7.6 Interrupt output (INT) The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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SDA output bank START condition register bank 0 R selected acknowledge from slave acknowledge ...
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SDA START condition write to port data out from port OE is LOW to observe a change in the outputs. Two, three, or four adjacent banks can be programmed ...
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SDA START condition R acknowledge from slave acknowledge from master data from register data from ...
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... NXP Semiconductors 9. Application design-in information V DD 1.6 kΩ 1.6 kΩ (optional) MASTER CONTROLLER SCL SDA RESET INT OE GND Device address configured as 0100 000X for this example. IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are configured as outputs. IO0_1, IO0_4, IO4_0 to IO4_7 configured as inputs. Fig 15. Typical application ...
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... NXP Semiconductors 10. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I I input current I V input/output voltage on any other pin I/O(n) V input/output voltage on pin IO0_n I/O(IO0n) I output current on an I/O pin ...
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... NXP Semiconductors Table 10. Static characteristics Symbol Parameter I LOW-level standby current stbL V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current L C input capacitance i I/Os V LOW-level input voltage ...
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... NXP Semiconductors Table 10. Static characteristics Symbol Parameter Inputs A0, A1 LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i [1] V must be lowered to 0 order to reset part. DD 12. Dynamic characteristics Table 11. Dynamic characteristics Symbol Parameter f SCL clock frequency ...
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... NXP Semiconductors Table 11. Dynamic characteristics Symbol Parameter Reset t reset pulse width w(rst) t reset recovery time rec(rst) t reset time rst [1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation. ...
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... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA Rise and fall times refer Fig 17. I C-bus timing diagram START SCL SDA RESET rec(rst) IOx_y Fig 18. Reset timing PCA9505_9506 Product data sheet bit 7 bit 6 MSB (A6) (A7 LOW HIGH 1 /f SCL ...
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... NXP Semiconductors 13. Test information Fig 19. Test circuitry for switching times PCA9505_9506 Product data sheet V I PULSE GENERATOR R = load resistance load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 0.85 mm terminal 1 index area terminal 1 56 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.30 mm 0.2 1 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 14. Acronym CDM DUT ESD HBM C-bus LED MM PLC POR PWM RAID PCA9505_9506 Product data sheet ...
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... NXP Semiconductors 18. Revision history Table 15. Revision history Document ID Release date PCA9505_9506 v.4 20100803 • Modifications: Table 10 “Static changing unit from “μA” to “mA” and specifying for 3 different voltages PCA9505_9506 v.3 20070606 PCA9506 v.2 20060509 PCA9506 v.1 20060214 (9397 750 14939) ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... PCA9505_9506 Product data sheet 40-bit I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Command register . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 7.3.1 IP0 to IP4 - Input Port registers . . . . . . . . . . . 10 7 ...