CS82C55AZ Intersil, CS82C55AZ Datasheet

IC I/O EXPANDER 24B 44PLCC

CS82C55AZ

Manufacturer Part Number
CS82C55AZ
Description
IC I/O EXPANDER 24B 44PLCC
Manufacturer
Intersil
Type
Programmable Peripheral Interfacer
Datasheets

Specifications of CS82C55AZ

Interface
Programmable
Number Of I /o
24
Interrupt Output
No
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Chip Configuration
8 Bit
Bus Frequency
8MHz
No. Of I/o's
24
Supply Voltage Range
4.5V To 5.5V
Digital Ic Case Style
LCC
No. Of Pins
44
Msl
MSL 3 - 168 Hours
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency - Clock
-
Lead Free Status / Rohs Status
RoHS Compliant part

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Part Number:
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Manufacturer:
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Quantity:
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CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may
be used with many different microprocessors. There are 24
I/O pins which may be individually programmed in 2 groups
of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Ordering Information
*Add “96” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CP82C55A-5
CP82C55A-5Z (Note)
CS82C55A-5*
CS82C55A-5Z* (Note)
IS82C55A-5*
IS82C55A-5Z* (Note)
5MHz
CP82C55A-5
CP82C55A-5Z CP82C55AZ (Note)
CS82C55A-5
CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ
IS82C55A-5
IS82C55A-5Z
MARKING
PART
PART NUMBERS
®
1
Data Sheet
CP82C55A
IP82C55A
IP82C55AZ (Note)
CS82C55A*
IS82C55A*
IS82C55AZ* (Note)
CQ82C55A*
CQ82C55AZ (Note)
IQ82C55A*
IQ82C55AZ* (Note)
ID82C55A
MD82C55A/B
8406602QA
8406602XA
8MHz
1-888-INTERSIL or 1-888-468-3774
CP82C55A
CP82C55AZ
IP82C55A
IP82C55AZ
CS82C55A*
IS82C55A*
IS82C55AZ
CQ82C55A*
CQ82C55AZ
IQ82C55A*
IQ82C55AZ
ID82C55A
MD82C55A/B
8406602QA
8406602XA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
MARKING
PART
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10μA
November 16, 2006
(See Ordering Info)
8MHz 80C86 and 80C88
RANGE (°C)
-55 to +125
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
TEMP.
SMD#
SMD#
All other trademarks mentioned are the property of their respective owners.
|
Copyright Intersil Americas Inc. 2002, 2005, 2006. All Rights Reserved
Intersil (and design) is a registered trademark of Intersil Americas Inc.
44 Ld PLCC
40 Ld PDIP
40 Ld PDIP (Pb-free)
40 Ld PDIP
40 Ld PDIP (Pb-free)
44 Ld PLCC (Pb-free)
44 Ld PLCC
44 Ld PLCC (Pb-free)
44 Ld MQFP
44 Ld MQFP (Pb-free)
44 Ld MQFP
44 Ld MQFP (Pb-free)
40 Ld CERDIP
44 Ld CLCC
PACKAGE
82C55A
E40.6
N44.65
Q44.10x10
F40.6
J44.A
FN2969.10
PKG. DWG. #

Related parts for CS82C55AZ

CS82C55AZ Summary of contents

Page 1

... PART 5MHz MARKING CP82C55A-5 CP82C55A-5 CP82C55A CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) IP82C55A IP82C55AZ (Note) CS82C55A-5* CS82C55A-5 CS82C55A* CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ IS82C55A-5* IS82C55A-5 IS82C55A* IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) CQ82C55A* CQ82C55AZ (Note) IQ82C55A* IQ82C55AZ* (Note) ID82C55A MD82C55A/B 8406602QA 8406602XA *Add “ ...

Page 2

Pinouts 82C55A (PDIP, CERDIP) TOP VIEW PA3 1 PA2 2 PA1 3 PA0 GND PC7 10 PC6 11 PC5 12 PC4 13 PC0 14 PC1 15 PC2 16 PC3 17 ...

Page 3

Pin Description SYMBOL TYPE The +5V power supply pin. A 0.1μF capacitor between GND GROUND D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET ...

Page 4

Functional Description Data Bus Buffer This three-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control ...

Page 5

Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. See Figure 2B. INPUT MODE ...

Page 6

The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will ...

Page 7

Mode 0 (Basic Input) RD INPUT CS, A1, A0 D7-D0 Mode 0 (Basic Output) WR D7-D0 CS, A1, A0 OUTPUT Mode 0 Configurations CONTROL WORD # ...

Page 8

Mode 0 Configurations (Continued) CONTROL WORD # 82C55A CONTROL WORD # ...

Page 9

Mode 0 Configurations (Continued) CONTROL WORD # 82C55A CONTROL WORD # ...

Page 10

STB IBF INTR RD INPUT FROM PERIPHERAL INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the condition: STB is a “one”, IBF ...

Page 11

WR OBF INTR ACK OUTPUT RD CONTROL WORD 1 PC6, PC7 1 = INPUT 0 = OUTPUT WR PORT A - (STROBED INPUT) PORT B - ...

Page 12

CONTROL WORD 1/0 1/0 1/0 FIGURE 11. MODE CONTROL WORD DATA FROM CPU TO 82C55A WR OBF INTR ACK STB IBF PERIPHERAL BUS RD NOTE: Any sequence where WR occurs ...

Page 13

MODE 2 AND MODE 0 (INPUT) CONTROL WORD 1/0 PC2-PC0 1 = INPUT 0 = OUTPUT RD WR MODE 2 AND MODE 1 (OUTPUT) CONTROL WORD D7 D6 ...

Page 14

MODE 0 IN PA0 In PA1 In PA2 In PA3 In PA4 In PA5 In PA6 In PA7 In PB0 In PB1 In PB2 In PB3 In PB4 In PB5 In PB6 In PB7 In PC0 In PC1 In PC2 ...

Page 15

Modes Port C generates or accepts “hand shaking” signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the “status” of each peripheral device and change the program flow ...

Page 16

INTERRUPT REQUEST PC3 PA0 R0 PA1 R1 PA2 R2 PA3 R3 DECODED PA4 R4 KEYBOARD PA5 R5 MODE 1 PA6 SHIFT (INPUT) PA7 CONTROL PC4 STROBE PC5 ACK 82C55A PB0 B0 PB1 B1 PB2 B2 BURROUGHS PB3 SELF-SCAN B3 PB4 ...

Page 17

INTERRUPT REQUEST PC3 PA0 D0 PA1 D1 PA2 D2 PA3 D3 CONTROLLER PA4 D4 PA5 D5 MODE 2 PA6 D6 PA7 D7 PC4 DATA STB PC5 ACK (IN) DATA READY PC7 PC6 ACK (OUT) 82C55A PC2 TRACK “0” SENSOR PC1 ...

Page 18

Absolute Maximum Ratings T = +25°C A Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 19

AC Electrical Specifications V SYMBOL PARAMETER READ TIMING (1) tAR Address Stable Before RD (2) tRA Address Stable After RD (3) tRR RD Pulse Width (4) tRD Data Valid From RD (5) tDF Data Float After RD (6) tRV Time ...

Page 20

Timing Waveforms RD INPUT CS, A1, A0 D7-D0 WR D7-D0 CS, A1, A0 OUTPUT STB IBF INTR RD INPUT FROM PERIPHERAL 20 82C55A tRR (3) tIR (13) tAR (1) tRD (4) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) tDW ...

Page 21

Timing Waveforms (Continued) WR OBF INTR ACK OUTPUT DATA FROM CPU TO 82C55A WR OBF INTR ACK STB IBF PERIPHERAL BUS RD NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF ...

Page 22

Timing Waveforms (Continued) A0-A1, CS tAW (7) DATA BUS tDW (10) WR tWW (9) FIGURE 30. WRITE TIMING AC Test Circuit V1 R1 OUTPUT FROM DEVICE UNDER TEST R2 NOTE: Includes STRAY and JIG Capacitance 22 82C55A A0-A1, CS tWA ...

Page 23

Burn-In Circuits CERDIP GND F10 ...

Page 24

Die Characteristics METALLIZATION: Type: Silicon - Aluminum ± Å Å Thickness: 11k 1k Metallization Mask Layout CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 24 82C55A GLASSIVATION: Type: SiO Thickness: 8k 82C55A RD PA0 PA1 PA2 PA3 PA4 ...

Page 25

Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...

Page 26

Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -D- -A- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...

Page 27

Ceramic Leadless Chip Carrier Packages (CLCC) 0.010 -E- 0.007 -H- - ...

Page 28

Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.042 (1.07) 0.048 (1.22) 0.056 (1.42) PIN (1) IDENTIFIER 0.050 (1.27 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN VIEW “A” ...

Page 29

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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