X96010V14IZ Intersil, X96010V14IZ Datasheet
X96010V14IZ
Specifications of X96010V14IZ
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X96010V14IZ Summary of contents
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... Ordering Information PART PART NUMBER MARKING X96010V14I X96010V I X96010V14IZ X96010VI Z (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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BLOCK DIAGRAM Reference VRef VSense SDA SCL WP A2, A1, A0 PIN ASSIGNMENTS TSSOP Pin Pin Name 1 A0 Device Address Select Pin 0. This pin determines the LSB of the device address required to com- municate using the 2-wire ...
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ABSOLUTE MAXIMUM RATINGS All voltages are referred to Vss. Temperature under bias ................... -65°C to +100°C Storage temperature ........................ -65°C to +150°C ................ -1.0V to +7V Voltage on every pin except Vcc Voltage on Vcc Pin .............................................0 to 5.5V D.C. ...
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ELECTRICAL CHARACTERISTICS All typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 3 in Control register ...
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D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions) Symbol Parameter IFS full scale current Offset D/A converter offset error DAC FSError D/A converter full scale error DAC DNL I1 or ...
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A/D CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions) Symbol Parameter ADCTIME A/D converter conversion time RIN VSense pin input ADC resistance CIN VSense pin input ADC capacitance VIN VSense input signal range ADC The ADC is monotonic Offset A/D ...
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INTERFACE A.C. CHARACTERISTICS Symbol Parameter f SCL Clock Frequency SCL (4) t Pulse width Suppression Time at IN inputs (4) t SCL Low to SDA Data Out Valid AA (4) t Time the bus free before start of new ...
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TIMING DIAGRAMS Figure 1. Bus Timing t F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT Figure 2. WP Pin Timing START SCL SDA IN WP Figure 3. Non-Volatile Write Cycle Timing SCL SDA 8th bit of ...
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... FSO = Full Scale Output, Ext = External, Int = Internal DEVICE DESCRIPTION The X96010 contains two independent Programmable Current Generators in one package. The combination of the X96010 functionality and Intersil’s QFN package lowers system cost, increases reliability, and reduces board space requirements. Two on-chip Programmable Current Generators may be independently programmed to either sink or source current ...
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PRINCIPLES OF OPERATION CONTROL AND STATUS REGISTERS The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96010. The X96010 contains seven Control, one Status, and several Reserved ...
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Figure 4. Control and Status Register Format Byte MSB Address 6 7 80h I2DS I1DS Non-Volatile I1 and I2 Direction 0: Source 1: Sink Direct Access to LUT1 81h Volatile or Reserved Reserved Non-Volatile Direct Access to LUT2 82h Volatile ...
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I2DS URRENT ENERATOR IRECTION ( VOLATILE The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to “0” (default), the Current Generator 2 of the X96010 is ...
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L2DAS: LUT2 IRECT CCESS ) VOLATILE When bit L2DAS is set to “0” (default), LUT2 is addressed by the output of the on-chip A/D converter. When bit L2DAS is set to “1”, LUT2 is addressed by bits ...
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VOLTAGE REFERENCE The voltage reference to the A/D and D/A converters on the X96010, may be driven from the on-chip volt- age reference, or from an external source via the VRef pin. Bit VRM in Control Register 0 selects between ...
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A/D Converter Range From Figure 6 we can see that the operating range of the A/D converter input depends on the voltage reference. The table below summarizes the voltage range restrictions on the VSense and VRef pins in different configurations ...
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Figure 7. D/A Converter Block Diagram VRef Voltage DAC1 or Divider DAC2 Input byte Figure 8. Look-up Table (LUT) Operation LUT2 Row Selection bits D0h LUT1 Row Selection bits 90h 16 X96010 Vcc Polarity I1DS or I2DS: bits 6 or ...
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By examining the block diagram in Figure 7, we see that the maximum current through pin I1 is set by fixing values for V(VRef) and R1. The output current can then be varied by changing the data byte at the ...
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D/A Converter 1 Access Summary L1DAS D1DAS Control Source 0 0 A/D converter through LUT1 (Default Bits L1DA5 - L1DA0 through LUT1 X 1 Bits D1DA7 - D1DA0 “X” = Don’t Care Condition (May be either “1” or ...
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Figure 10. D/A Converter Power-on Reset Response Voltage V ADCOK 0V Current I x 10% x Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH ...
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Figure 11. Valid Start and Stop Conditions SCL SDA Figure 12. Valid Data Changes on the SDA Bus SCL SDA Figure 13. Acknowledge Response From Receiver SCL from Master SDA Output from Transmitter SDA Output from Receiver START 20 X96010 ...
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X96010 Memory Map The X96010 contains a 144 byte array of mixed vola- tile and nonvolatile memory. This array is split up into three distinct parts, namely: (Refer to figure 14.) – Look-up Table 1 (LUT1) – Look-up Table 2 ...
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Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to figure 15.). This byte includes three parts: – The four MSBs (SA7 - SA4) are the Device Type Identifier, which must always be ...
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Figure 17. Byte Write Sequence Signals from the Master Signal at SDA Signals from the Slave Page Write Operation The 144-byte memory array is physically realized as one contiguous array, organized as 9 pages of 16 bytes each. “Page Write” ...
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Figure 19. Example: Writing 12 bytes to a 16-byte page starting at location 11. 7 bytes Address = 0 The four registers Control 1 through 4, have a nonvol- atile and a volatile cell for each bit. At power-up, the ...
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Figure 21. Read Sequence S Slave Signals t Address from the a with Master r R Signal SDA Signals from the Slave The Data Bytes are from the memory location indicated ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...