AD9804AJSTRL

Manufacturer Part NumberAD9804AJSTRL
DescriptionIC CCD SIGNAL PROC 10BIT 48-LQFP
ManufacturerAnalog Devices Inc
TypeCCD Signal Processor, 10-Bit
AD9804AJSTRL datasheets

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Specifications of AD9804AJSTRL

Rohs StatusRoHS non-compliantInput TypeLogic
Output TypeLogicInterface3-Wire Serial
Mounting TypeSurface MountPackage / Case48-LQFP
Current - Supply-  
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FEATURES
18 MSPS Correlated Double Sampler (CDS)
6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Preblanking Function
10-Bit 18 MSPS A/D Converter
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power CMOS
48-Lead LQFP Package
APPLICATIONS
PC Cameras
Digital Still Cameras
PRODUCT DESCRIPTION
The AD9804 is a complete analog signal processor for CCD
applications. It features an 18 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9804’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled VGA, black level clamp, and a 10-bit A/D
converter. The internal VGA gain register is programmed through
a 3-wire serial digital interface.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Complete 10-Bit 18 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
PBLK
AVDD
AVSS
6dB TO 40dB
CDS
VGA
CCDIN
CLP
10
CLPDM
VGA GAIN
REGISTER
AD9804
DIGITAL
INTERFACE
SL
SCK
SDATA
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
AD9804
CLPOB
DRVDD
CLP
DRVSS
10
10-BIT
DOUT
ADC
VR
BANDGAP
T
REFERENCE
VRB
INTERNAL
CML
BIAS
DVDD
INTERNAL
DVSS
TIMING
SHP SHD DATACLK
© Analog Devices, Inc., 2000

AD9804AJSTRL Summary of contents

  • Page 1

    FEATURES 18 MSPS Correlated Double Sampler (CDS 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Preblanking Function 10-Bit 18 MSPS A/D Converter 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power ...

  • Page 2

    AD9804–SPECIFICATIONS ANALOG SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION MAXIMUM CLOCK RATE CORRELATED DOUBLE SAMPLER (CDS) 1 Allowable CCD Reset Transient 1 Max Input Range before Saturation 1 Max CCD Black Pixel ...

  • Page 3

    TIMING SPECIFICATIONS (C Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK Hi/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth 1 CLPOB Pulsewidth SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay ...

  • Page 4

    AD9804 CONNECT Pin No. Mnemonic Type 1, 2, 18, 24 34, 36, 45 3–12 D0– DRVDD P 14 DRVSS P 15, 41, 42, 44 DVSS P 16 DATACLK DI 17, 40 DVDD ...

  • Page 5

    TIMING DIAGRAMS CCD SIGNAL SHP t S1 SHD t INH DATACLK t OD OUTPUT N–10 DATA NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. ...

  • Page 6

    AD9804 PROGRAMMING THE SERIAL INTERFACE Table I. VGA Gain Register Contents (Default Value x096) MSB RNW ADDRESS BITS 0 SDATA ...

  • Page 7

    VARIABLE GAIN AMPLIFIER (VGA) OPERATION DETAILS The VGA stage provides a gain range dB, pro­ grammable with 10-bit resolution through the serial digital interface. The minimum gain needed to match a ...

  • Page 8

    AD9804 SERIAL INTERFACE (LSB) D0 (MSB DATA OUTPUTS DRIVER SUPPLY 3V ANALOG SUPPLY 0.1�F 10k� 1.0�F 1.0�F 1.0�F 3 0.1� PIN 1 ...