AD9806KST

Manufacturer Part NumberAD9806KST
DescriptionIC CCD SIGNAL PROC 10BIT 48-LQFP
ManufacturerAnalog Devices Inc
TypeCCD Signal Processor, 10-Bit
AD9806KST datasheets

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Specifications of AD9806KST

Rohs StatusRoHS non-compliantInput TypeLogic
Output TypeLogicInterface3-Wire Serial
Mounting TypeSurface MountPackage / Case48-LQFP
Analog Front End TypeCCDAnalog Front End CategoryVideo
Interface TypeSerial (3-Wire)Input Voltage Range0.5V
Operating Supply Voltage (min)2.7VOperating Supply Voltage (typ)3.3V
Operating Supply Voltage (max)3.6VResolution10b
Number Of Adc's1Power Supply TypeAnalog/Digital
Operating Temp Range-20C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count48
Package TypeLQFPNumber Of Channels1
Current - Supply-  
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AD9806
REGISTER DESCRIPTION
(a) A-REGISTER: Modes of Operation
a1
a0
Modes
0
0
ADC-MODE
0
1
AUX-MODE
1
0
AUXMID-MODE
1
1
CCD-MODE
(b) B-REGISTER: Output Modes
b1
b0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Normal
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
High Impedance
(c) C-REGISTER: Clock Modes
c1 c0
SHP-SHD Clock Pulses
0
0
Active Low
0
1
Active Low
1
0
Active High
1
1
Active High
(d) D-REGISTER: Power-Down Modes
Modes
d1
d0 Description
Normal
0
0
Normal Operation
High Speed
0
1
High-Speed AUX/ADC-MODE
Power-Down1
1
0
Reference Stand-By (Same
Mode as STBY Pin 18)
Power-Down2
1
1
Total Shut-Down
(e) E-REGISTER: Clamp Level Selection
e1
e0
Clamp Level
CLP (0)
0
0
32 LSBs
CLP (1)
0
1
48 LSBs
CLP (2)
1
0
64 LSBs
CLP (3)
1
1
16 LSBs
(f) F-REGISTER: CCD-Mode PGA
f 9 f8 f 7 f6 f5 f4 f 3 f 2 f 1 f 0
Gain (0)
0 0
0 0 0 0
0 0 0
Gain (1023) 1 1
1 1 1 1
1 1 1
f) F-REGISTER: AUXMID-Mode PGA
(Power-On Default
Value = 11)
Gain (512) 1 0 0 0 0 0 0 0 0 0
Gain (1023) 1 1 1 1 1 1 1 1 1 1
Only the 9 LSBs of F-REG are used to adjust gain.
(f) F-REGISTER: AUX-Mode PGA
(Default = 00)
Gain (128) 1 0 0 0 0 0 0 0
Gain (255) 1 1 1 1 1 1 1 1
0
1
0
1
(g) G-REGISTER: DAC1 Input
1
0
1
0
Code (0)
Code (255) 1 1 1 1 1 1 1 1
(Default = 00)
Clamp Active Pulses
(h) H-REGISTER: DAC2 Input
Active Low
Active High
Active Low
Code (0)
Active High
Code (255) 1 1 1 1 1 1 1 1
(Default = 00)
(j) J-REGISTER: Even-Odd Offset Correction
j0
0
1
(m) M-REGISTER: DAC1 and DAC2 PDN
m0
0
(Default = 00)
1
NOTE: With the exception of a write to the PGA register dur-
ing AUX-mode, all data writes must be 10 bits. During an
AUX-mode write to the PGA register, only 8 bits of data are
required. If more than 14 SCK rising edges are applied during a
write operation, additional SCK pulses will be ignored (see
Figure 9). All reads must be 10 bits to receive valid register
(Default = 00 . . . 0)
contents. All registers default to 0s on power-up, except for the
A-register which defaults to 11. Thus, on power-up, the AD9806
CCD–Gain
defaults to CCD mode with the 8-bit DACs powered down. Dur-
ing the power-up phase, it is recommended that SL be HIGH
0
Minimum
and SCK be LOW to prevent accidental register write operations.
1
Maximum
SDATA may be unknown. The RNW bit (“Read/Not Write”)
must be LOW for all write operations to the serial interface, and
HIGH when reading back from the serial interface registers.
(Default = 00 . . . 0)
f 9 f8 f 7 f 6 f5 f 4 f 3 f 2 f 1 f 0 AUXMID–Gain
–4 dB
+14 dB
(Default = 00 . . . 0)
f 9 f8 f 7 f 6 f5 f 4 f 3 f 2
AUX-Gain
Minimum
Maximum
(Default = 00 . . . 0)
g7 g6 g5 g4 g3 g2 g1 g0
DAC1 Output
0 0 0 0 0 0 0 0
Minimum
Maximum
(Default = 00 . . . 0)
h7 h6 h5 h4 h3 h2 h1 h0
DAC2 Output
0 0 0 0 0 0 0 0
Minimum
Maximum
(Default = 0)
Even-Odd Offset Correction
Offset Correction In Use
Offset Correction Not Used
(Default = 0)
Power-Down of 8-Bit DACs
8-Bit DACs Powered Down
8-Bit DACs Operational

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