AD9806KST

Manufacturer Part NumberAD9806KST
DescriptionIC CCD SIGNAL PROC 10BIT 48-LQFP
ManufacturerAnalog Devices Inc
TypeCCD Signal Processor, 10-Bit
AD9806KST datasheets

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Specifications of AD9806KST

Rohs StatusRoHS non-compliantInput TypeLogic
Output TypeLogicInterface3-Wire Serial
Mounting TypeSurface MountPackage / Case48-LQFP
Analog Front End TypeCCDAnalog Front End CategoryVideo
Interface TypeSerial (3-Wire)Input Voltage Range0.5V
Operating Supply Voltage (min)2.7VOperating Supply Voltage (typ)3.3V
Operating Supply Voltage (max)3.6VResolution10b
Number Of Adc's1Power Supply TypeAnalog/Digital
Operating Temp Range-20C to 85COperating Temperature ClassificationCommercial
MountingSurface MountPin Count48
Package TypeLQFPNumber Of Channels1
Current - Supply-  
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TIMING SPECIFICATIONS
CCD
N
SHP
t
INHIBIT
SHD
ADCCLK
t
OD
N–0
D0–D9
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY IS 9 CYCLES.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
N
VIDEO
INPUT
ADCCLK
t
HOLD
N–9
D0–D9
EFFECTIVE
PIXELS
CCD
SIGNAL
CLPOB
CLPDM
PBLK
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPDM OVERWRITES PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
N+1
N+2
t
ID
t
ID
t
HOLD
ADCCLK RISING EDGE PLACEMENT
N–9
N–8
N+1
N+2
N+3
t
OD
t
ID
N–8
N–7
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
BLANKING
OPTICAL BLACK
INTERVAL
AD9806
N+3
N+4
N–7
N–6
N–5
t
).
INHIBIT
N+5
N+4
N–6
N–5
EFFECTIVE
DUMMY BLACK
PIXELS

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