AD9843AJSTZ Analog Devices Inc, AD9843AJSTZ Datasheet

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AD9843AJSTZ

AD9843AJSTZ
Manufacturer Part Number	AD9843AJSTZ
Description	IC CCD SIGNAL PROC 10BIT 48-LQFP
Manufacturer	Analog Devices Inc
Type	CCD Signal Processor, 10-Bit
AD9843AJSTZ datasheets	1. AD9843AJST.pdf (16 pages)

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Warranty: 60 days

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Specifications of AD9843AJSTZ
Input Type	Logic	Output Type	Logic
Interface	3-Wire Serial	Mounting Type	Surface Mount
Package / Case	48-LQFP	Analog Front End Type	CCD
Analog Front End Category	Video	Interface Type	Serial (3-Wire)
Operating Supply Voltage (min)	2.7V	Operating Supply Voltage (typ)	3.3V
Operating Supply Voltage (max)	3.6V	Resolution	10b
Number Of Adc's	1	Power Supply Type	Analog/Digital
Operating Temp Range	-20C to 85C	Operating Temperature Classification	Commercial
Mounting	Surface Mount	Pin Count	48
Package Type	LQFP	Number Of Channels	1
Lead Free Status / RoHS Status	Lead free / RoHS Compliant	Current - Supply	-

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PBLK

CCDIN

CLPDM

AUX1IN

AUX2IN

CLP

AD9843A

PRODUCT DESCRIPTION

The AD9843A is a complete analog signal processor for CCD

applications. It features a 20 MHz single-channel architecture

designed to sample and condition the outputs of interlaced and

progressive scan area CCD arrays. The AD9843A’s signal chain

consists of an input clamp, correlated double sampler (CDS),

digitally controlled variable gain amplifier (VGA), black level

clamp, and 10-bit A/D converter. Additional input modes are

provided for processing analog video signals.

The internal registers are programmed through a 3-wire serial

digital interface. Programmable features include gain adjust-

ment, black level adjustment, input configuration, and power-

down modes.

The AD9843A operates from a single 3 V power supply, typi-

cally dissipates 78 mW, and is packaged in a 48-lead LQFP.

FUNCTIONAL BLOCK DIAGRAM

AVDD

AVSS

4dB 6dB

2dB~36dB

CDS

2:1

VGA

MUX

CLP

2:1

BUF

MUX

INTERNAL

REGISTERS

DIGITAL

INTERFACE

SCK

SDATA

Complete 10-Bit 20 MSPS

CCD Signal Processor

AD9843A

CLPOB

DRVDD

CLP

DRVSS

10-BIT

DOUT

ADC

VRT

BANDGAP

REFERENCE

VRB

OFFSET

DAC

INTERNAL

CML

BIAS

DVDD

INTERNAL

DVSS

TIMING

SHP

SHD

DATACLK

Download datasheet (161Kb)

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AD9843AJSTZ Summary of contents
Page 1 PBLK CCDIN CLPDM AUX1IN AUX2IN CLP AD9843A PRODUCT DESCRIPTION The AD9843A is a complete analog signal processor for CCD applications. It features a 20 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan ... Page 2 AD9843A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale ... Page 3 CCD-MODE SPECIFICATIONS Parameter P OWER CONSUMPTION MAXIMUM CLOCK RATE CDS 1 Allowable CCD Reset Transient 1 Max CCD Black Pixel Amplitude 1 Max Input Range Before Saturation Max Input Range Before Saturation Max Input Range Before Saturation Max Output Range ... Page 4 AD9843A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS ... Page 5 TIMING SPECIFICATIONS Serial Timing in Figures 8–10.) Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth 1 CLPOB Pulsewidth SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD ... Page 6 AD9843A CONNECT Pin Number Name 1, 2 DRVSS 3–12 D0–D9 13 DRVDD 14 DRVSS 15, 18, 24, 41 DVSS 16 DATACLK 17 DVDD1 19 PBLK 20 CLPOB 21 SHP 22 SHD 23 CLPDM 25, 26, 35 AVSS ... Page 7 DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit ... Page 8 Performance Characteristics AD9843A 100 SAMPLE RATE – MHz 0.5 0.25 0 –0.25 –0.5 0 200 400 600 4 3 ... Page 9 CCD-MODE AND AUX-MODE TIMING CCD SIGNAL SHP t S1 SHD t INH DATACLK t OD OUTPUT N–10 DATA NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP ... Page 10 AD9843A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Register Address Name Operation Channel Select CCD/AUX VGA Gain LSB Clamp Level LSB Control CDS ... Page 11 Table II. Operation Register Contents (Default Value x000) D10 Must be set to zero. Set to one. Table III. VGA Gain Register Contents (Default Value x096) MSB D10 ... Page 12 AD9843A DC RESTORE 0.1 F CCDIN CLPDM CIRCUIT DESCRIPTION AND OPERATION The AD9843A signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data. DC Restore To ... Page 13 CLPOB or separately. The CLPDM pulse should be a minimum of four pixels wide. Variable Gain Amplifier The VGA stage provides a gain range dB, program- mable with 10-bit resolution through the serial ... Page 14 AD9843A 0.8V ??V 0.1 F INPUT SIGNAL 0.4V AUX2IN VIDEO SIGNAL 0.1 F MSB D10 CCD V OUT V-DRIVE 0.4V 0dB TO 36dB 5k AUX1IN VGA 10 ... Page 15 APPLICATIONS INFORMATION The AD9843A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the AD9843A analog input through a ... Page 16 AD9843A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75 0.018 (0.45 TOP VIEW (PINS DOWN) COPLANARITY 12 25 0.003 (0.08 MIN ...

AD9843AJSTZ Summary of contents

Page 1
PBLK CCDIN CLPDM AUX1IN AUX2IN CLP AD9843A PRODUCT DESCRIPTION The AD9843A is a complete analog signal processor for CCD applications. It features a 20 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan ...
Page 2
AD9843A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale ...
Page 3
CCD-MODE SPECIFICATIONS Parameter P OWER CONSUMPTION MAXIMUM CLOCK RATE CDS 1 Allowable CCD Reset Transient 1 Max CCD Black Pixel Amplitude 1 Max Input Range Before Saturation Max Input Range Before Saturation Max Input Range Before Saturation Max Output Range ...
Page 4
AD9843A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS ...
Page 5
TIMING SPECIFICATIONS Serial Timing in Figures 8–10.) Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth 1 CLPOB Pulsewidth SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD ...
Page 6
AD9843A CONNECT Pin Number Name 1, 2 DRVSS 3–12 D0–D9 13 DRVDD 14 DRVSS 15, 18, 24, 41 DVSS 16 DATACLK 17 DVDD1 19 PBLK 20 CLPOB 21 SHP 22 SHD 23 CLPDM 25, 26, 35 AVSS ...
Page 7
DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit ...
Page 8
Performance Characteristics AD9843A 100 SAMPLE RATE – MHz 0.5 0.25 0 –0.25 –0.5 0 200 400 600 4 3 ...
Page 9
CCD-MODE AND AUX-MODE TIMING CCD SIGNAL SHP t S1 SHD t INH DATACLK t OD OUTPUT N–10 DATA NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP ...
Page 10
AD9843A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Register Address Name Operation Channel Select CCD/AUX VGA Gain LSB Clamp Level LSB Control CDS ...
Page 11
Table II. Operation Register Contents (Default Value x000) D10 Must be set to zero. Set to one. Table III. VGA Gain Register Contents (Default Value x096) MSB D10 ...
Page 12
AD9843A DC RESTORE 0.1 F CCDIN CLPDM CIRCUIT DESCRIPTION AND OPERATION The AD9843A signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data. DC Restore To ...
Page 13
CLPOB or separately. The CLPDM pulse should be a minimum of four pixels wide. Variable Gain Amplifier The VGA stage provides a gain range dB, program- mable with 10-bit resolution through the serial ...
Page 14
AD9843A 0.8V ??V 0.1 F INPUT SIGNAL 0.4V AUX2IN VIDEO SIGNAL 0.1 F MSB D10 CCD V OUT V-DRIVE 0.4V 0dB TO 36dB 5k AUX1IN VGA 10 ...
Page 15
APPLICATIONS INFORMATION The AD9843A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the AD9843A analog input through a ...
Page 16
AD9843A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75 0.018 (0.45 TOP VIEW (PINS DOWN) COPLANARITY 12 25 0.003 (0.08 MIN ...

AD9843AJSTZ

AD9843AJSTZ

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Specifications of AD9843AJSTZ

Related parts for AD9843AJSTZ

AD9843AJSTZ Summary of contents

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