LMH0030VS/NOPB National Semiconductor, LMH0030VS/NOPB Datasheet

LMH0030VS/NOPB

Manufacturer Part Number

LMH0030VS/NOPB

Description

IC SERIALIZER VID DGTL 64-TQFP

Manufacturer

National Semiconductor

Series

LMH®r

Datasheet

1.LMH0030VSNOPB.pdf (30 pages)

Specifications of LMH0030VS/NOPB

Function

Serializer

Data Rate

1.485Gbps

Input Type

CMOS

Output Type

CMOS

Number Of Inputs

Number Of Outputs

Voltage - Supply

2.5V, 3.3V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

64-TQFP, 64-VQFP

Input Voltage

3.3 V

Supply Voltage (max)

3.45 V

Supply Voltage (min)

3.15 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

For Use With

SD130EVK - BOARD EVALUATION LMH0030

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

*LMH0030VS/NOPB
LMH0030VS

Available stocks

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Manufacturer

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Price

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Bonase Electronics (HK) Co., Limited

Part Number:

LMH0030VS/NOPB

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Company:

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LMH0030VS/NOPB

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LMH0030

SMPTE 292M/259M Digital Video Serializer with Video and

Ancillary Data FIFOs and Integrated Cable Driver

General Description

The LMH0030 SMPTE 292M/259M Digital Video Serializer

with Ancillary Data FIFO and Integrated Cable Driver is a

monolithic integrated circuit that encodes, serializes and

transmits bit-parallel digital video data conforming to SMPTE

125M and 267M standard definition, 10-bit wide component

video and SMPTE 260M, 274M, 295M and 296M high-defi-

nition, 20-bit wide component video standards. The LMH0030

operates at SMPTE 259M serial data rates of 270 Mbps, 360

Mbps, the SMPTE 344M serial data rate of 540 Mbps, and the

SMPTE 292M serial data rates of 1483.5 and 1.485 Gbps.

The serial data clock frequency is internally generated and

requires no external frequency setting, trimming or filtering

components.

The LMH0030 performs functions which include: parallel-to-

serial data conversion, SMPTE standard data encoding, NRZ

to NRZI data format conversion, serial data clock generation

and encoding with the serial data, automatic video rate and

format detection, ancillary data packet management and in-

sertion, and serial data output driving. The LMH0030 has

circuitry for automatic EDH/CRC character and flag genera-

tion and insertion per SMPTE RP-165 (standard definition) or

SMPTE 292M (high definition). Optional LSB dithering is im-

plemented which prevents pathological pattern generation.

Unique to the LMH0030 are its video and ancillary data FI-

FOs. The video FIFO allows the video data to be delayed from

0 to 4 parallel data clock periods for video timing purposes.

The ancillary data port and on-chip FIFO and control circuitry

store and insert ancillary flags, data packets and checksums

into the ancillary data space. The LMH0030 also has an ex-

clusive built-in self-test (BIST) and video test pattern gener-

ator (TPG) with SD and HD component video test patterns:

reference black, PLL and EQ pathologicals and color bars in

4:3 and 16:9 raster formats for NTSC and PAL standards*.

The color bar patterns feature optional bandwidth limiting

coding in the chroma and luma transitions.

The LMH0030 has a unique multi-function I/O port for imme-

diate access to control and configuration settings. This port

may be programmed to provide external access to control

functions and indicators as inputs and outputs. The designer

can thus customize the LMH0030 to fit the desired applica-

tion. At power-up or after a reset command, the LMH0030 is

auto-configured to a default operating condition. Separate

power pins for the output driver, PLL and the serializer im-

prove power supply rejection, output jitter and noise perfor-

mance.

Order Number LMH0030VS

201803

64-Pin TQFP

The LMH0030's internal circuitry is powered from +2.5V and

the I/O circuitry from a +3.3V supply. Power dissipation is

typically 430mW at 1.485 Gbps including two 75Ω AC-cou-

pled and back-matched output loads. The device is packaged

in a 64-pin TQFP.

Features

■

* Patent applications made or pending.

Applications

■

SDTV/HDTV serial digital video standard compliant

Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps

and 1.485 Gbps SDV data rates with auto-detection

Low output jitter: 125ps max, 85ps typical

Low power: typically 430mW

No external serial data rate setting or VCO filtering

components required*

Fast PLL lock time: < 150µs typical at 1.485 Gbps

Adjustable depth video FIFO for timing alignment

Built-in self-test (BIST) and video test pattern generator

(TPG)*

Automatic EDH/CRC word and flag generation and

insertion

On-chip ancillary data FIFO and insertion control circuitry

Flexible control and configuration I/O port

LVCMOS compatible data and control inputs and outputs

75Ω ECL-compatible, differential, serial cable-driver

outputs

3.3V I/O power supply and 2.5V logic power supply

operation

64-pin TQFP package

SDTV/HDTV parallel-to-serial digital video interfaces for:

— Video cameras

— VTRs

— Telecines

— Digital video routers and switchers

— Digital video processing and editing equipment

— Video test pattern generators and digital video test

— Video signal generators

equipment

NS Package Number VEC-64A

October 10, 2008

www.national.com

Related parts for LMH0030VS/NOPB

LMH0030VS/NOPB Summary of contents

Page 1

... Order Number LMH0030VS © 2008 National Semiconductor Corporation The LMH0030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is typically 430mW at 1.485 Gbps including two 75Ω AC-cou- pled and back-matched output loads ...

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Typical Application www.national.com 2 20180301 ...

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Block Diagram 3 20180302 www.national.com ...

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Connection Diagram www.national.com 64-Pin TQFP Order Number LMH0030VS See NS Package Number VEC-64A 4 20180303 ...

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Absolute Maximum Ratings It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semicon- ductor Sales Office / Distributors for availability and specifi- cations. CMOS ...

Page 6

Symbol Parameter I (2.5V) Power Supply Current, 2.5V DD Supply, Total I (2.5V) Power Supply Current, 2.5V DD Supply, Total AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter f Parallel Video ...

Page 7

Test Loads Timing Jitter Bandpass 7 20180304 20180306 www.national.com ...

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Test Circuit www.national.com 8 20180307 ...

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Timing Diagram Device Operation The LMH0030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts par- allel SDTV or HDTV component digital video signals into serial ...

Page 10

ACLK when it is being used for control register access. When theANC/CTRL input is a logic-high, ACLK affects only the ancillary data FIFO operation. When the ANC/CTRL input is a logic-low, ACLK affects only the control register opera- tion. ...

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ACLK. Observe the port input hold timing specification. Example: Setup (without enabling) the TPG Mode via the AD port using the 1125 line, 30 frame, 74.25MHz, interlaced com- ...

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MULTI-FUNCTION I/O PORT The Multi-function I/O port can be configured to provide im- mediate access to many control and indicator functions within the LMH0030 configuration and control registers. The indi- vidual pins comprising this port may be assigned as input ...

Page 13

This is done so that information like line numbering can be cor- rectly inserted. The PLL itself will have locked in 200 mi- croseconds (HD rates) or less. ...

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It is strongly recommended that V be applied until device initialization and configuration is com- pleted. Example: Enable ...

Page 15

TABLE 1. Configuration and Control Data Register Summary Register Function Bits EDH Error (SD) 1 Full-Field Flags 5 Active Picture Flags 5 ANC Flags 5 EDH Force 1 EDH Enable 1 F/F Flag Error 1 A/P Flag Error 1 ANC ...

Page 16

Register Function Bits NRZI_Enable 1 LSB_Clipping 1 SYNC_Detect_Enabl 1 e I/O Bus Pin Config. 48 Note 12: Connected to multifunction I/O port at power-on. Note 13 logic-1, OFF = logic-0 (positive logic). Bit 7 Bit 6 EDH 0 ...

Page 17

Bit 7 Bit 6 TEST PASS/FAIL TPG ENABLE PATTERN SELECT(5) VIDEO INFO 0 (register address 0Eh) VERT. DITHER VPG FILTER DITHER ENABLE ENABLE ENABLE MULTI-FUNCTION I/O BUS PIN CONFIGURATION I/O PIN 0 CONFIG (register address 0Fh) reserved reserved PIN 0 ...

Page 18

TABLE 3. Control Register Addresses Address Register Name Decimal EDH 0 1 EDH 1 2 EDH 2 3 ANC 0 4 ANC 1 5 ANC 2 6 ANC 3 7 ANC 4 8 ANC 5 23 ANC 6 24 SWITCH ...

Page 19

DIDs (or DID ranges) into the FIFO. Similarly, the ANC MASK[15: 8-bit word that can be used to selec- tively control loading of packets with specific SDID or DBNs (or SDID or DBN ranges). When ANC MASK[7:0] ...

Page 20

Format Code Format Specification [4,3,2,1,0] 01010 SDTV, 36 ITU-R BT 601.5 01011 SDTV, 27 ITU-R BT 601.5 10001 HDTV, 74.25 SMPTE 260M 10010 HDTV, 74.25 SMPTE 274M 10011 HDTV, 74.25 SMPTE 274M 11001 HDTV, 74.25 SMPTE 274M 11010 HDTV, 74.25 ...

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Pin # SEL[5] in each register indicates whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured ...

Page 22

Test Pattern Bit 5 Select Word Bits > 1=HD Video Raster Standard 0=SD 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black 1 PLL Path Path. 1 color Bars 1 1125 Line, 74.25 MHz, 30 ...

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Test Pattern Bit 5 Select Word Bits > 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black 0 PLL Path Path. 0 color Bars (SD 0 BIST) 625 Line, 25 Frame, 27 MHz, PAL 4x3 ...

Page 24

TABLE 6. I/O Configuration Register Addresses for Control Register Functions Register Bit [5] [4] reserved Flag Error Flag Error 0 0 ANC Flag 0 0 Error CRC Error 0 0 (SD/HD) Addresses x05h through ...

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Register Bit [5] [4] Dither Enable 1 0 FIFO Insert 1 0 Enable Bit Address Pin # SEL [n] [3] [2] [ Power-On I/P or O/P Status [0] 1 Input 1 Input www.national.com ...

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Pin Descriptions Pin Name 1 V DDPLLD 2 V SSPLLD 3 IO0 4 IO1 5 DV0 6 DV1 7 DV2 8 DV3 9 DV4 10 V SSD 11 DV5 12 DV6 13 DV7 14 DV8 15 DV9 16 V DDD ...

Page 27

Pin Name 49 RD/WR 50 ANC/CTRL 51 V DDSD 52 R PRE REF 53 R LVL REF 54 V SSSD 55 V SSSD 56 SDO 57 V DDLS 58 SDO 59 V SSLS 60 V DDZ 61 V SSPLLA 62 ...

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Application Information Complete details for the SD130ASM evaluation PCB are available on National’s WEB site. This circuit demonstrates the capabilities of the LMH0030 and allows its evaluation in a native configuration. An assembled demonstration board kit, part number SD130EVK, complete ...

Page 29

Physical Dimensions inches (millimeters) unless otherwise noted 64-Pin TQPF Order Number LMH0030VS NS Package Number VEC-64A 29 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...

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