PCA9515ADP,118 NXP Semiconductors, PCA9515ADP,118 Datasheet - Page 5

• Manufacturer Part Number: PCA9515ADP,118
• Description: IC I2C BUS REPEATER 8-TSSOP
• Manufacturer: NXP Semiconductors
• Type: Repeaterr

Specifications of PCA9515ADP,118

• Package / Case: 8-TSSOP
• Tx/rx Type: I²C Logic
• Delay Time: 113ns
• Capacitance - Input: 6pF
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 800µA
• Mounting Type: Surface Mount
• Logic Family: PCA9515A
• Operating Supply Voltage: 2.3 V to 3.6 V
• Power Dissipation: 100 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1032-2; 935275998118; PCA9515ADP-T

NXP Semiconductors
7. Application design-in information
PCA9515A_4
Product data sheet
A typical application is shown in
on a 3.3 V I
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9515A is pulled LOW by a device on the I
hysteresis type input detects the falling edge and causes the internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9515A will typically be at V
In order to illustrate what would be seen in a typical application, refer to
Figure
we would see the waveform shown in
transmission until the falling edge of the 8
the data line (SDA) while the slave pulls it LOW through the PCA9515A. Because the V
of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen. After the master
has transmitted the 9
On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset
from ground equal to the V
be pulled to the V
important to note that any arbitration or clock stretching events on bus 1 require that the
V
by the PCA9515A and then transmitted to bus 0.
Fig 4.
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of the PCA9515A (see V
6. If the bus master in
Typical application
2
C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz
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MASTER
400 kHz
BUS
of the slave device, which is very close to ground in this example. It is
th
SDA
SCL
clock pulse, the slave releases the data line.
Rev. 04 — 11 April 2008
10 k
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bus 0
3.3 V
Figure 4
of the PCA9515A. After the 8
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V
Figure
10 k
ILc
= 0.5 V.
in
SDA0
SCL0
EN
Figure 5
were to write to the slave through the PCA9515A,
Section 9 “Static
4. In this example, the system master is running
V
PCA9515A
CC
th
clock pulse. At that point, the master releases
on bus 0. This looks like a normal I
SDA1
SCL1
10 k
characteristics”) to be recognized
bus 1
5 V
th
10 k
clock pulse the data line will
SDA
SCL
100 kHz
SLAVE
002aad739
PCA9515A
2
C-bus, a CMOS
© NXP B.V. 2008. All rights reserved.
Figure 5
I
2
C-bus repeater
and
2
C-bus
5 of 18
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