PCA9508D,112 NXP Semiconductors, PCA9508D,112 Datasheet

IC I2C/SMBUS BIDIR-REPEAT 8SOIC

PCA9508D,112

Manufacturer Part Number
PCA9508D,112
Description
IC I2C/SMBUS BIDIR-REPEAT 8SOIC
Manufacturer
NXP Semiconductors
Type
Repeaterr
Datasheet

Specifications of PCA9508D,112

Tx/rx Type
I²C Logic
Delay Time
170ns
Capacitance - Input
5.2pF
Voltage - Supply
2.7 V ~ 5.5 V
Current - Supply
170mA
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Function
I2C Bus Repeater
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
SO
Pin Count
8
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935285665112
PCA9508D
PCA9508D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9508D,112
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
The PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and
provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to
5.5 V) for I
features of the I
I
lines, thus enabling two buses of 400 pF. Using the PCA9508 enables the system
designer to isolate two halves of a bus for both voltage and capacitance, and perform
hot-swap and voltage level translation. Furthermore, the dual supply pins can be powered
up in any sequence; when any of the supply pins are unpowered, the 5 V tolerant I/O are
high-impedance.
The hot swap feature allows an I/O card to be inserted into a live backplane without
corrupting the data and clock buses. Control circuitry prevents the backplane from being
connected to the card until a stop command or bus idle occurs on the backplane without
bus contention on the card. Zero offset output voltage allows multiple PCA9508s to be put
in series and still maintains an excellent noise margin.
PCA9508 has B side and A side bus drivers. The 2.7 V to 5.5 V bus B side drivers behave
much like the drivers on the PCA9515A device, while the adjustable voltage bus A side
drivers drive more current and incur no static offset voltage. This results in a LOW on the
B side translating into a nearly 0 V LOW on the A side.
The static offset design of the B side PCA9508 I/O drivers prevents them from being
connected to another device that has a rise time accelerator including the PCA9510/A,
PCA9511/A, PCA9512/A, PCA9513/A, or PCA9514/A or a static offset voltage including
the PCA9507 (B side), PCA9508 (B side), PCA9509 (A side), PCA9515/A, PCA9516A,
PCA9517/A (B side), PCA9518, PCA9519 (A side), or P82B96/PCA9600 (Sx/Sy side).
The A side of two or more PCA9508s can be connected together, however, to allow a star
topology with the A side on the common bus, and the A side can be connected directly to
any other buffer with static or dynamic offset voltage. Multiple PCA9508s can be
connected in series, A side to B side, with no build-up in offset voltage with only
time-of-flight delays to consider.
The PCA9508 drivers are not enabled unless the bus is idle, V
V
system control. Caution should be observed to only change the state of the enable pin
when the bus is idle.
The output pull-down on the B side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
2
C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL)
CC(B)
PCA9508
Hot swappable level translating I
Rev. 01 — 28 April 2008
is above 2.5 V. The EN pin can also be used to turn the drivers on and off under
2
C-bus or SMBus applications. While retaining all the operating modes and
2
C-bus system during the level shifts, it also permits extension of the
2
C-bus repeater
CC(A)
Product data sheet
is above 0.8 V and

Related parts for PCA9508D,112

PCA9508D,112 Summary of contents

Page 1

PCA9508 Hot swappable level translating I Rev. 01 — 28 April 2008 1. General description The PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and provides level shifting between low voltage (down to 0.9 V) and ...

Page 2

... NXP Semiconductors This prevents a lock-up condition from occurring. The output pull-down on the A side drives a hard LOW and the input level is set at 0.5V lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V. Table 1 Table 1. Feature V range (V) CC(A) ...

Page 3

... NXP Semiconductors 3. Ordering information Table 2. Ordering information +85 C. amb Type number Topside Package mark Name PCA9508D PCA9508 SO8 PCA9508DP 9508 TSSOP8 [1] Also known as MSOP8. 4. Functional diagram PCA9508 SDAA SCLA V CC(B) pull-up resistor 0.55V / CC 0.45V CC UVLO 100 s DELAY EN Fig 1. Functional diagram of PCA9508 ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning V Fig 2. 5.2 Pin description Table 3. Symbol V CC(A) SCLA SDAA GND EN SDAB SCLB V CC(B) 6. Functional description Refer to The PCA9508 enables I without degradation of system performance. The PCA9508 contains two bidirectional open-drain buffers specifically designed to provide superior hot-swap and/or support up-translation/down-translation between the low voltage (as low as 0 ...

Page 5

... NXP Semiconductors HIGH long enough to complete the initialization state (t the SDA and SCL pins have been HIGH for the bus idle time or when all pins are HIGH and a STOP condition is seen on the SDAA and SCLA pins, SDAA is connected to SDAB and SCLA is connected to SCLB. ...

Page 6

... NXP Semiconductors 2 6.5 I C-bus systems As with the standard I HIGH levels on the buffered bus (standard open-collector configuration of the I The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. This part designed to work with Standard-mode and Fast-mode I only specify 3 mA output drive ...

Page 7

... NXP Semiconductors On the B bus side of the PCA9508, the clock and data lines would have a positive offset from ground equal to the V be pulled to the V the end of the acknowledge, the level rises only to the LOW level set by the driver in the PCA9508 for a short delay while the A bus side rises above 0.5V HIGH ...

Page 8

... NXP Semiconductors SDAA SDA SCLA SCL BUS hot-swap PCA9508 MASTER and offset free EN Fig 6. Typical series application SCL SDA Fig 7. SCL SDA Fig 8. PCA9508_1 Product data sheet Hot swappable level translating SDAB SDAA SDAB SCLB SCLA SCLB hot-swap PCA9508 and offset free ...

Page 9

... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage port B CC(B) V supply voltage port A CC(A) V voltage on an input/output pin I/O I input current I P total power dissipation tot T storage temperature stg ...

Page 10

... NXP Semiconductors Table 5. Static characteristics 5.5 V; GND = Symbol Parameter Input and output SDAA and SCLA V HIGH-level input voltage IH V LOW-level input voltage IL V input clamping voltage IK I input leakage current LI I LOW-level input current IL V LOW-level output voltage OL I HIGH-level output leakage current ...

Page 11

... NXP Semiconductors 10. Dynamic characteristics Table 6. Dynamic characteristics 5.5 V; GND = Symbol Parameter t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay PHL t LOW to HIGH output transition time A side; TLH t HIGH to LOW output transition time A side; THL t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay ...

Page 12

... NXP Semiconductors 10.1 AC waveforms input 1 PHL 80 % 0.6 V output THL Fig 9. Propagation delay and transition times; B side to A side Fig 11. Propagation delay; B side to A side PCA9508_1 Product data sheet Hot swappable level translating I 3.0 V 1 PLH 1 0 TLH 002aad642 Fig 10. Propagation delay and transition times; ...

Page 13

... NXP Semiconductors wait 200 s EN SDAA SCLB SDAB SCLA Fig 12. t timing connect EN SCLB SDAB SDAA SCLA Fig 13. t timing idle(connect) Fig 14. t timing stop(connect) PCA9508_1 Product data sheet Hot swappable level translating SCLA t connect 0 V move until SCLA goes LOW ...

Page 14

... NXP Semiconductors 11. Test information Fig 15. Test circuit for open-drain outputs PCA9508_1 Product data sheet Hot swappable level translating I PULSE GENERATOR R = load resistor; 1. side; 167 load capacitance includes jig and probe capacitance termination resistance should be equal Rev. 01 — 28 April 2008 PCA9508 V CC(B) ...

Page 15

... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 16

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 17

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 18

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 19

... NXP Semiconductors Fig 18. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 9. Acronym CDM CMOS DUT ESD HBM 2 I C-bus I SMBus 15. Revision history Table 10. ...

Page 20

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 21

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 A side to B side 6.2 B side to A side 6.3 Weak drive on B side . . . . . . . . . . . . . . . . . . . . 5 6.4 Enable pin (EN 6.5 I C-bus systems ...

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