SLXT914QC.B3 Intel, SLXT914QC.B3 Datasheet - Page 16

• Manufacturer Part Number: SLXT914QC.B3
• Description: IC QUAD ETHERNET REPEATER 100QFP
• Manufacturer: Intel
• Type: Repeaterr

Specifications of SLXT914QC.B3

• Rohs Status: RoHS non-compliant
• Tx/rx Type: Ethernet
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 180mA
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Delay Time: -
• Capacitance - Input: -
• Other names: 831521

Intel
2.4
2.4.1
31-Oct-2005
16
®
LXT914 Flexible Quad Ethernet Repeater
The shared functional blocks of the LXT914 Repeater are controlled by the global state machine
(Figure
of the IEEE 802.3 standard.
The LXT914 Repeater also implements the Partition State Diagram as defined by the IEEE 802.3
standard and shown in
64.
The CCLimit value sets the number of consecutive collisions that must occur before the port is
subjected to automatic partitioning. Auto-partition/re-connection is also supported by the
LXT914 Repeater with Tw5 conforming to the standard requirement of 450 to 560 bit times.
Initialization
The following description applies to the initial power-on reset and to any subsequent hardware
reset. When a reset occurs (RESET pin pulled High for > 1 ms), the device senses the levels at the
various control pins (see
LEDs, and the AUI port functions.
Local Management Mode Initialization
An internal pull-up causes the LXT914 Repeater to default to the Local management mode unless
the LOC/EXT pin is tied Low. In the Local mode the serial port is a unidirectional interface used
only to download setup parameters from an external device.
In a Locally managed multiple-repeater (daisy chain) configuration, the first repeater in the chain
performs special functions. The First Position Select (FPS) pin is used to establish position (FPS
High = First, FPS Low = Not First). After establishing the Hardware mode, each LXT914 Repeater
monitors the FPS pin to determine its position.
If FPS is High (First Position), the repeater performs the following functions:
Outputs a 1 MHz Serial Clock (SCLK). SCLK is derived from the 20 MHz SYSCLK input in
ASYNC mode and from BCLKIO in SYNC mode; it is supplied to the SCLK inputs of all other
repeaters on the bus and to the EEPROM.
Asserts Chip Select (CS) High to enable the EEPROM.
Outputs a serial 9-bit request-to-send (RTS) strobe. The programmable device responds to the RTS
strobe with a serial data stream containing the setup parameters for all repeaters in the chain.
Clocks the first 48 serial data input (SDI) bits from the EEPROM into its setup register. Refer to
Table 9
Asserts Serial Enable Output (SENO) Low to enable the next repeater in line.
The second repeater has FPS tied Low and Serial Enable Input (SENI) connected to the Serial
Enable Output (SENO) of the first repeater. When enabled by a Low on SENI, each repeater
downloads its portion of the stream, then stops accepting data and asserts SENO Low. The SENO
pin is linked to the SENI input of the next repeater. This enables the next repeater to clock in its 48-
bit word and so on.
If FPS is Low (Not First Position), the repeater performs the following functions:
3). This diagram and all associated notations used are in strict accordance with section 9.6
and
Table 10
Intel
for Setup Register bit assignments.
Figure
®
Order Number: 248989, Revision: 003
Figure
LXT914 Flexible Quad Ethernet Repeater
4. The value of CCLimit as implemented in the LXT914 Repeater is
3) to determine the correct operating modes for Management,
Datasheet