SLXT915QC.B3 Intel, SLXT915QC.B3 Datasheet - Page 12

no-image

SLXT915QC.B3

Manufacturer Part Number
SLXT915QC.B3
Description
IC QUAD ETHERNET REPEATER 64-QFP
Manufacturer
Intel
Type
Repeaterr
Datasheet

Specifications of SLXT915QC.B3

Rohs Status
RoHS non-compliant
Tx/rx Type
Ethernet
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
240mA
Mounting Type
Surface Mount
Package / Case
64-QFP
Delay Time
-
Capacitance - Input
-
Lead Free Status / Rohs Status
Not Compliant
Other names
831529
Intel
2.2.3.1
2.2.3.2
2.3
12
®
LXT915 Simple Quad Ethernet Repeater
Note:
limited by bus loading factors such as parasitic capacitance. The IRB can be operated
synchronously or asynchronously. Refer to
signal descriptions.
Synchronous IRB Operation
In the synchronous mode, a common external source provides the 10 MHz backplane clock
(BCLKIO) and the 20 MHz system clock (SYSCLK) to all repeaters. (BCLKIO must be
synchronous to SYSCLK and may be derived from SYSCLK using a divide-by-two circuit.) In the
synchronous mode 32 or more LXT915s may be connected on the IRB, providing 128 10BASE-T
ports and 32 AUI ports.
Asynchronous IRB Operation
In the asynchronous mode an external BCLKIO source is not required. The repeaters run
independently until one takes control of the IRB. The transmitting repeater then outputs its own 10
MHz clock onto the BCLKIO line. All other repeaters sync to that clock for the duration of the
transmission. In the asynchronous mode, 12 or more LXT915s may be connected to the IRB,
providing 48 10BASE-T ports and 12 AUI ports.
The maximum number of repeaters which may be linked on the backplane is limited by board
design factors. The numbers listed above are engineering estimates only. Stronger drivers and
reduced capacitive loading in PCB layout may allow an increased device count.
Internal Repeater Circuitry
The basic repeater circuitry is shared among all the ports within the LXT915. It consists of a global
repeater state machine, several timers and counters and the timing recovery circuit. The timing
recovery circuit includes a FIFO for retiming and recovery of the clock which is used to clock the
receive data out onto the IRB.
The shared functional blocks of the LXT915 are controlled by the global state machine shown in
Figure
the IEEE 802.3 standard.
The LXT915 also implements the Partition State Diagram as defined by the IEEE 802.3 standard
and shown in
The CC
subjected to automatic partitioning. Auto-partition/reconnection is also supported by the
LXT915 with Tw5 conforming to the standard requirement of 450 to 560 bit times.
3. This diagram and all associated notations used are in strict accordance with section 9.6 of
LIMIT
Figure
value sets the number of consecutive collisions that must occur before the port is
4. The value of CC
LIMIT
Table 3
as implemented in the LXT915 is 64.
for control signals and to
Table 4
for IRB
Datasheet

Related parts for SLXT915QC.B3