IC I2C MUX 2CH 8-SOIC

PCA9540BD,118

Manufacturer Part NumberPCA9540BD,118
DescriptionIC I2C MUX 2CH 8-SOIC
ManufacturerNXP Semiconductors
PCA9540BD,118 datasheet
 


Specifications of PCA9540BD,118

Package / Case8-SOIC (3.9mm Width)Applications2-Channel I²C Multiplexer
InterfaceI²CVoltage - Supply2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Mounting TypeSurface MountProductDecoders, Encoders, Multiplexers & Demultiplexers
Number Of Lines (input / Output)2.0 / 1.0Propagation Delay Time0.3 ns at 2.3 V to 5.5 V
Supply Voltage (max)5.5 VSupply Voltage (min)2.3 V
Maximum Operating Temperature+ 85 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTNumber Of Input Lines2.0
Number Of Output Lines1.0Lead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With568-3615 - DEMO BOARD I2COther names568-1844-2
935276035118
PCA9540BD-T
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PCA9540B
2-channel I
Rev. 04 — 3 September 2009
1. General description
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I
The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time, determined by the contents of the
programmable control register.
A power-on reset function puts the registers in their default state and initializes the I
state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the V
limit the maximum high voltage that will be passed by the PCA9540B. This allows the use
of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
can pull the bus up to the desired voltage level for this channel. All I/O pins are 5 V
tolerant.
2. Features
I
1-of-2 bidirectional translating multiplexer
I
2
I
C-bus interface logic; compatible with SMBus standards
I
Channel selection via I
I
Power up with all multiplexer channels deselected
I
Low R
I
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I
No glitch on power-up
I
Supports hot insertion
I
Low standby current
I
Operating power supply voltage range of 2.3 V to 5.5 V
I
5 V tolerant inputs
I
0 Hz to 400 kHz clock frequency
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD2-A115
and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8, TSSOP8, XSON8U
2
C-bus multiplexer
2
C-bus
switches
on
Product data sheet
2
C-bus.
2
C-bus
pin can be used to
DD

PCA9540BD,118 Summary of contents

  • Page 1

    PCA9540B 2-channel I Rev. 04 — 3 September 2009 1. General description The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels. Only one SCx/SDx ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Ordering information +85 C amb Type number Topside Package mark Name PCA9540BD PA9540B SO8 PCA9540BDP 9540B TSSOP8 PCA9540BGD 40B XSON8U 4. Block diagram SD0 SD1 SC0 SC1 SCL SDA Fig 1. PCA9540B_4 Product data sheet Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package ...

  • Page 3

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 4. 5.2 Pin description Table 2. Symbol SCL SDA V DD SD0 SC0 V SS SD1 SC1 PCA9540B_4 Product data sheet 1 8 SCL SC1 2 7 SDA SD1 PCA9540BD SD0 4 5 SC0 002aae713 Pin configuration for SO8 ...

  • Page 4

    ... NXP Semiconductors 6. Functional description Refer to 6.1 Device addressing Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9540B is shown in Fig 5. The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation ...

  • Page 5

    ... NXP Semiconductors Table 6.3 Power-on reset When power is applied reset condition until V and the PCA9540B registers and I states (all zeroes), causing all the channels to be deselected. Thereafter, V lowered below 0 reset the device. 6.4 Voltage translation The pass gate transistors of the PCA9540B are constructed such that the V ...

  • Page 6

    ... NXP Semiconductors Figure 7, we see that V 3 lower so the PCA9540B supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see More Information can be found in application note AN262, “PCA954X family of I multiplexers and switches” . ...

  • Page 7

    ... NXP Semiconductors 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL ...

  • Page 8

    ... NXP Semiconductors 7.5 Bus transactions SDA START condition Fig 12. Write control register SDA START condition Fig 13. Read control register 8. Application design-in information Fig 14. Typical application PCA9540B_4 Product data sheet slave address R/W slave address SDA SDA SCL SCL 2 I C-bus/SMBus master ...

  • Page 9

    ... NXP Semiconductors 9. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to ground (V Symbol tot T stg T amb [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C ...

  • Page 10

    ... NXP Semiconductors 10. Static characteristics Table 5. Static characteristics +85 C; unless otherwise specified. SS amb See Table 6 for Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage ...

  • Page 11

    ... NXP Semiconductors Table 6. Static characteristics +85 C; unless otherwise specified. SS amb See Table 5 for Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage ...

  • Page 12

    ... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START HD;STA condition t LOW period of the SCL clock LOW t HIGH period of the SCL clock ...

  • Page 13

    ... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 15. Definition of timing on the I PCA9540B_4 Product data sheet HD;DAT HIGH SU;DAT 2 C-bus Rev. 04 — 3 September 2009 PCA9540B 2 2-channel I C-bus multiplexer t t HD;STA SU;STA SU;STO Sr 002aaa986 © NXP B.V. 2009. All rights reserved. ...

  • Page 14

    ... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 15

    ... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 16

    ... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 18. Package outline SOT996-2 (XSON8U) ...

  • Page 17

    ... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 18

    ... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

  • Page 19

    ... NXP Semiconductors Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 10. Acronym CDM ESD HBM 2 I C-bus I/O IC LSB MM POR SMBus PCA9540B_4 Product data sheet ...

  • Page 20

    ... NXP Semiconductors 15. Revision history Table 11. Revision history Document ID Release date PCA9540B_4 20090903 • Modifications: Added XSON8U package offering (affects information”, PCA9540B_3 20090528 PCA9540B_2 20040929 (9397 750 13731) PCA9540B_1 20040413 (9397 750 12918) PCA9540B_4 Product data sheet Data sheet status Product data sheet Section 2 “ ...

  • Page 21

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 22

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 4 6.3 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.4 Voltage translation . . . . . . . . . . . . . . . . . . . . . . Characteristics of the I 7 ...