PCA9540BD,118 NXP Semiconductors, PCA9540BD,118 Datasheet - Page 6

• Manufacturer Part Number: PCA9540BD,118
• Description: IC I2C MUX 2CH 8-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9540BD,118

• Package / Case: 8-SOIC (3.9mm Width)
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Number Of Lines (input / Output): 2.0 / 1.0
• Propagation Delay Time: 0.3 ns at 2.3 V to 5.5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 2.0
• Number Of Output Lines: 1.0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1844-2; 935276035118; PCA9540BD-T

NXP Semiconductors
7. Characteristics of the I
PCA9540B_4
Product data sheet
7.1 Bit transfer
7.2 START and STOP conditions
Figure
3.5 V or lower so the PCA9540B supply voltage could be set to 3.3 V. Pull-up resistors can
then be used to bring the bus voltages to their appropriate levels (see
More Information can be found in application note AN262, “PCA954X family of I
multiplexers and switches” .
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 8.
Fig 9.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
7, we see that V
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
Rev. 04 — 3 September 2009
S
o(sw)(max)
9).
will be at 2.7 V when the PCA9540B supply voltage is
data valid
data line
stable;
Figure
allowed
change
of data
8).
2-channel I
STOP condition
PCA9540B
mba607
2
Figure
P
C-bus multiplexer
© NXP B.V. 2009. All rights reserved.
mba608
14).
2
C/SMBus
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