PCA9541D/03,118 NXP Semiconductors, PCA9541D/03,118 Datasheet
PCA9541D/03,118
Specifications of PCA9541D/03,118
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PCA9541D/03-T
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PCA9541D/03,118 Summary of contents
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PCA9541 2-to-1 I Rev. 07 — 2 July 2009 1. General description The PCA9541 is a 2-to C-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. ...
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... NXP Semiconductors An active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin LOW resets the I does the internal Power-On Reset (POR) function. 2. Features I 2-to-1 bidirectional master selector C-bus interface logic; compatible with SMBus standards I PCA9541/01 powers up with Channel 0 selected ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information +85 C amb Type number Package Name PCA9541D/01 SO16 PCA9541PW/01 TSSOP16 PCA9541BS/01 HVQFN16 PCA9541D/03 SO16 PCA9541PW/03 TSSOP16 PCA9541BS/03 HVQFN16 5. Marking Table 2. Type number PCA9541D/01 PCA9541PW/01 PCA9541BS/01 PCA9541D/03 PCA9541PW/03 PCA9541BS/03 PCA9541_7 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset Description plastic small outline package ...
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... NXP Semiconductors 6. Block diagram PCA9541 SCL_MST0 SDA_MST0 RESET POWER-ON RESET V DD SCL_MST1 SDA_MST1 INT0 INT1 Fig 1. Block diagram of PCA9541 PCA9541_7 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset INPUT STOP FILTER DETECTION 2 I C-BUS CONTROL AND REGISTER ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning 1 INT0 2 SDA_MST0 SCL_MST0 3 RESET 4 PCA9541D/01 PCA9541D/03 5 SCL_MST1 SDA_MST1 6 INT1 002aab379 Fig 2. Pin configuration for SO16 Fig 4. Pin configuration for HVQFN16 PCA9541_7 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset ...
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... NXP Semiconductors 7.2 Pin description Table 3. Symbol INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 SCL_SLAVE SDA_SLAVE INT_IN V DD [1] HVQFN16 package die supply ground is connected to both the and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region ...
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... NXP Semiconductors 8. Functional description Refer to 8.1 Device address Following a START condition, the upstream master that wants to control the I make a status check must send the address of the slave it is accessing. The slave address of the PCA9541 is shown in resistors are incorporated on the hardware selectable pins and they must be pulled HIGH or LOW ...
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... NXP Semiconductors • During a write operation, the PCA9541 will acknowledge bytes sent to the IE and CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since read-only register. The 2 LSBs of the Command Code do not roll over to 00b but stay at 10b. ...
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... NXP Semiconductors • master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that longer connected to the downstream bus. This is indicated by setting the BUSLOST bit in the Interrupt Status Register. ...
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... NXP Semiconductors The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to be activated for a ‘functional interrupt test’. Remark: The regular way to proceed is that a master asks to take the control of the bus by programming MYBUS and BUSON bits based on NMUYBUS and NBUSON values. ...
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... NXP Semiconductors Table 6. Register 0 - Interrupt Enable (IE) register bit description Legend: * default value Bit Symbol Access Value 1 BUSINITMSK R/W 0 INTINMSK R/W [1] Default values are the same for PCA9541/01 and PCA9541/03. 8.3.2 Register 1: Control Register (B1:B0 = 01b) The Control Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Control Registers, one for each upstream channel ...
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... NXP Semiconductors Table master reads its Control Register NMYBUS [1] MYBUS and NMYBUS is an exclusive-OR type function where: Equal values (00b or 11b) means that the master reading its Control Register has control of the bus. Different values (01b or 10b) means that the master reading its Control Register does not have control of the bus ...
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... NXP Semiconductors Table 11. Default Control Register values Type version Master Bit 7 NTESTON TESTON PCA9541/01 MST_0 0 MST_1 0 PCA9541/03 MST_0 0 MST_1 0 Table 12 master device wants to take control of the I function of the current I Control Register. Current status of the I NBUSON is one of the following: • The master reading its Control Register does not have control and the I • ...
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Table 12. Bus control sequence Read Control Register performed by the master Byte Status NBUSON BUSON NMYBUS MYBUS Byte [1] read Hex 0 bus off has control bus off no control bus off no ...
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... NXP Semiconductors 8.4 Interrupt Status registers The PCA9541 provides 4 different types of interrupt: • To indicate to the former I • To indicate to the new I – The bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). – A ‘bus not well initialized’ condition has been detected by the PCA9541 when the switch has been done (built-in bus recovery/initialization not active) ...
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... NXP Semiconductors 8.4.3 Downstream interrupt An interrupt can also be generated by a downstream device by asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to ‘1’ by either master, INT0 and INT1 both go LOW. By setting the INTINMSK bit to ‘1’ master and/or the INTINMSK bit to ‘1’ by the other master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does (do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW) ...
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... NXP Semiconductors Table 14. Register 2 - Interrupt Status (ISTAT) register bit description Legend: * default value Bit Symbol Access Value [4] 2 BUSOK R only [4] 1 BUSINIT R only [2] 0 INTIN R only [1] Default values are the same for PCA9541/01 and PCA9541/03. [2] Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if: ...
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... NXP Semiconductors 8.6 External reset A reset can be accomplished by holding the RESET pin LOW for a minimum of t PCA9541 registers and I RESET input is once again HIGH. This input typically requires a pull-up resistor to V Default states are: • C-bus upstream Channel 0 connected to the I PCA9541/01 • ...
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... NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors 9.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL ...
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... NXP Semiconductors 9.5 Bus transactions slave address START condition R/W acknowledge from slave Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit Remark third data byte is sent, it will not be acknowledged by the PCA9541. slave address START condition ( 00: Interrupt Enable register ...
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SDA_MST0 slave address command code register START condition R/W auto increment acknowledge from slave SCL_MST0 INT1 SCL_SLAVE SDA_SLAVE INT0 MASTER 1 ...
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... NXP Semiconductors (1) SDA_MST0 slave address START condition R/W acknowledge from slave SCL_MST0 INT1 INT0 MASTER 1 has control of the bus (1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus). ...
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... NXP Semiconductors 10. Application design-in information 3.3 V 3.3 V Fig 17. Typical application 10.1 Specific applications The PCA9541 is a 2-to C-bus applications, where continuous maintenance and control monitoring is required even if one master fails or its controller card is removed for maintenance. The PCA9541 can also be used in other applications, such as where masters share the same resource but cannot share the same bus gatekeeper multiplexer in long single bus applications bus initialization/recovery device ...
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... NXP Semiconductors 10.2 High reliability systems In a typical multipoint application, shown in primary and back-up) are located on separate I downstream I to provide high reliability of the I Fig 18. High reliability backplane application 2 I C-bus commands are sent via the primary or back-up master and either master can take command of the I the other master is disabled or removed from the system ...
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... NXP Semiconductors 10.3 Masters with shared resources Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541 can be used to separate the masters, as shown in Field Replaceable Unit (FRU) EEPROMs or temperature sensors. Fig 20. Masters with shared resources application 10 ...
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... NXP Semiconductors Fig 21. Gatekeeper multiplexer application 10.5 Bus initialization/recovery to initialize slaves without hardware reset 2 If the I C-bus is hung, I and Slave 2 in PCA9541/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (for example, Slave 0). The bus master can then ...
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... NXP Semiconductors 11. Limiting values Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol tot T stg T amb [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C ...
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... NXP Semiconductors Table 16. Static characteristics Symbol Parameter Select inputs A0 to A3, INT_IN, RESET V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i Pass gate R ON-state resistance on V switch output voltage o(sw) I leakage current L INT0 and INT1 outputs ...
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... NXP Semiconductors 13. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL f SCL clock frequency SCL(init/rec) (bus initialization/bus recovery) t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t LOW period of the SCL clock ...
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... NXP Semiconductors [ total capacitance of one bus line in pF. b [5] Measurements taken with 1 k pull-up resistor and 50 pF load. [6] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. [7] Upon reset, the full delay will be the sum of t SDA ...
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... NXP Semiconductors START SCL SDA RESET 50 % INTn Fig 25. Definition of RESET timing 14. Test information Fig 26. Test circuitry for switching times PCA9541_7 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset REC;STA V I PULSE GENERATOR Definitions test circuit Load resistance. ...
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... NXP Semiconductors 15. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 20. Acronym AI CDM DUT EEPROM ESD FRU HBM 2 I C-bus IC MM POR RC SMBus ...
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... NXP Semiconductors 18. Revision history Table 21. Revision history Document ID Release date PCA9541_7 20090702 • Modifications: Type numbers PCA9541D//02, PCA9541PW/02 and PCA9541BS/02 are withdrawn; this affects: – Section 1 “General – Section 2 – Table 1 “Ordering information” – Table 2 “Marking codes” – ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Command Code . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3 Interrupt Enable and Control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 ...